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How to Achieve Concurrency in SystemVerilog Testbench?
SystemVerilog testbench components run concurrently, and concurrent components run as separate threads. The threads are spawned, coordinated, and synchronized. They typically share the state information of a process, and share memory and other resources directly. A DV simulator can only execute one thread at a time in a single-core CPU. Multiple threads waiting to execute…
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How to Enforce SystemVerilog Constrant Solver Order?
Inside a constraint block, there is NO implied order of how the variable values will be solved. The SystemVerilog constraint solver is free to choose the variables to randomize first. Let us look at an example below. The intention is to randomize “addrType” first, and then randomize “addr” value per “addrType”. However, the constraint solver…
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Will Overclocking the Design Speed Up the DV Simulation?
Some engineers may think, increasing clock frequency, or overclocking the design can speed up DV simulation. This would be wrong. Modern simulation tools are discrete-event based. They model the operation of the design as a sequence of events in time. Each event occurs at a particular timestamp and marks a change of design states. Between…
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Unpacked Arrays in SystemVerilog Testbench
There are 4 types of unpacked arrays commonly used in SystemVerilog testbench: The following shows how to instantiate these unpacked arrays The table below shows a comparison across all array types above, especially in terms of performance: Type Memory Index Application & Performance Fixed Size Allocated at compile-time; unchangeable afterwards Numerical Gives the best performance;…
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How to implement hardware for a 3-number sorter?
If sorting of 3 numbers must complete in 1 cycle, then the optimal solution is to use 3 comparators. The diagram below shows the implementation: This design can easily be pipelined, if timing becomes an issue. If it is not required to get the array sorted in a single cycle, then the above implementation can…
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A Recommended Reading: “Metal ECO implementation using Mask Programmable cells”
Metal ECO is vital to absorb late design changes before tapeout. It could save millions of dollars in mask cost. Traditionally, metal ECO takes advantage of spare functional cells sprinkled across the design during the physical design phase. However, traditional metal ECO has inherent limitations: it is not possible to include all cell types as…
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What should you ask the interviewer at the end of an interview?
An interview runs in two ways: while the interviewer is testing you and evaluating your potential, you should also assess if the team is suitable for you. You should typically expect a question from your interviewer at the end of each interview: “any questions for me”. This is the opportunity to express your interests in…
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Leverage “Behavioral Interview for Software Engineers” for Hardware Interviews
In hardware interviews, it is not uncommon to cover behavioral questions. In fact, quite a few companies, such as Amazon, Intel and Apple, specifically have behavioral interviews. To succeed in hardware interviews, candidates should master both technical and behavioral questions. Although no specific books exist for hardware engineers to prepare behavioral interviews, one dedicated for…
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What to Do If Setup Time and Hold Time Have Conflicts?
It is not uncommon to see setup time and hold time conflicting in STA. It could be caused by: Some timing paths may only face one factor, while the other paths may see multiple factors. Timing paths with setup time and hold time conflicting can be categorized into 3 groups: Group 1 and 2 are…
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How to Deal with Noise / Crosstalk in Physical Design?
In our book “Crack the Hardware Interview – Physical Design & Silicon Debug”, we discussed that noise fix is an essential step during timing ECOs. We will dive a little deeper into this topic. What is Noise / Crosstalk? Noise / crosstalk analysis is a type of signal integrity analysis completed during physical design. When…
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