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Published: The 2nd Edition of Our Book Series “Crack the Hardware Interview”
We are thrilled to announce that, the second edition of “Crack the Hardware Interview” is released! We published the first edition of this book series in early 2024, and received quite a few positive feedback. The second edition is still structured in the same way as how the modern ASIC / VLSI industry partitions the…
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How can latch arrays save power? How do they work?
In the digital design world, data storages in magnitude of MegaBytes (MB), KiloBytes (KB) and Bytes (B), are typically implemented using DRAM, SRAM and flops, respectively. Flop arrays, in particular, can sometimes be replaced with latch arrays, to optimize power. An Idea and A Concept Conceptually, a posedge triggered flop consists of a low-transparent latch…
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How to Eliminate Metastability Caused by Reset Removal?
In practice, reset assertion is asynchronous and de-assertion is synchronous. Synchronous reset de-assertion can make sure flops are under metastability after reset removal. However, due to place and route, reset de-assertion does not happen simultaneously for all flops in an SoC. RTL designers must be cautious when dealing with reset de-assertion. There are several steps…
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How to Boost Emulation Performance & Efficiency?
Emulation is commonly used in hardware verification and validation. Unlike simulation where all RTL / hardware activities are modeled in software domain, emulation is running on both software and hardware. The table below shows a comparison between RTL / hardware simulation and emulation: Simulation Emulation Speed Slow Often 1000x faster than simulation Cost Lower Professional…
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How does Synthesis Tool do Boundary Optimization?
Boundary Optimization is a synthesis optimization technique to exploit functional constraints across design hierarchies. Boundary Optimization includes the following: The diagram below shows each of the above techniques. Note, optimizations within the sub-design are not considered as Boundary Optimizations, for example, constant and unloaded register removal if the source of the constant / unloaded is…
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Design a DDR Memory Controller (V) – Timing Parameters
Before the memory control issues a command to DDR devices, it checks if certain timing parameters are met, otherwise the DDR device cannot work properly. There are tons of timing parameters in JEDEC standards, and each DDR generation / device type could have different timing requirements. Fortunately, from DDR controller’s perspective, only 4 major categories…
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How to Verify SRAMs are Integrated Properly?
SRAMs are widely used in SOC design. To verify SRAMs are integrated into the design properly, design engineers should write SVAs wherever SRAMs are used, or embed SVAs in SRAM wrappers. These SVAs will eventually be used in DV simulation and FV. In functional mode, these SVAs may include: In low-power mode, these SVAs may…
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What If an RTL Bug is Found after RTL Freeze?
It is not uncommon to find RTL bugs after RTL freeze. Typically after RTL freeze, DV and FV team will continue running regressions, and a corner-case RTL bug might be uncovered at this point. The first step would be figuring out the exact reproducing recipe, and summarizing what conditions or scenarios would sensitize the bug.…
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How to do Inter-Thread Communications (ITC) in SystemVerilog Testbench?
In SystemVerilog testbench, concurrent threads require communication to establish control of sequence of execution. There are 3 types of inter-thread communications (ITC): Event-based ITC Synchronized operation of concurrent threads is achieved via event variables: a thread waits for an event to be triggered, and an executing thread triggers the event to enable the waiting thread…
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