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Mastering Specification Writing in AI Era: Precise Inputs Matter More Than Ever
We are entering the AI era where natural language is the primary interface for system architecture, chip design, and verification. With AI models turning natural language prompts directly into RTL and test benches, the quality of your output is strictly bounded by the quality of your specification (or spec). Specs written by non-trained authors have…
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Why does floorplan require designer feedback?
Floorplan is required for topographical synthesis / production synthesis, as well as physical design. It often requires designer feedback due to the following reasons. Synthesis Re-spin Time There are quite a few factors impacting synthesis re-spin time, such as timing closure difficulty, logic levels, logic complexity, etc. Two most important factors are standard cell area…
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Best Practice for SVA Naming Conventions
Consistent SVA naming conventions not just improve code quality, but also make FV setup more easily, for example: When designers need to convert a group of assume properties to assertion properties When designers need to disable or waive certain groups of properties We show a sample SVA naming convention checklist below: SVA Naming Convention Comment…
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How to write efficient DV constraints?
Split Bigger Problem into Smaller Ones Instead of mixing everything together, splitting bigger problems into smaller steps offers better performance. One may consider using “Solve-Before” for user defined solving order. In addition, it is also recommended to sequence constraint solving in “pre_randomize()” and “post_randomize()” whenever possible. Use “Solve-Before” with Caution Although user-defined “solve-before” constructs are…
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What can cause a simulation hang?
Simulation hang is a condition where simulator functionalities cannot advance. We can only observe that nothing meaningful has happened for a long time. Simulation hang can be caused by RTL bugs, testbench (TB) issues, or C-model errors. RTL Bugs A combinational loop in RTL can prevent time from advancing. When there exists a combinational loop…
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How to spot toxic managers before accepting an offer?
Most people only realize the manager is toxic after on-boarding, when the switching costs are too high. They did not realize, toxic managers often reveal themselves during the interview process, if they know what to ask and what to look for. Patterns of Toxic Managers The most common type of toxic managers looks like this:…
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What are LEC abort points? How to debug aborts?
It is not uncommon to see abort points during LEC. They are the key points that have not been proven either equivalent or non-equivalent based on the current tool settings, such as compare effort or compare algorithms. There are several possible causes of abort points: Don’t Care conditions, such as out-of-range index and X-assignments. They…
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How to improve re-build time during test case development?
During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are several ways to optimize re-build time during test case development.…
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How to resolve SVA false failure with gated clocks?
In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: “config_regs” can legally be changed when “block_busy” is low, during which the gated clock does not toggle and the SVA does not check its consequent “$stable(config_regs)”. When the next time “block_busy” is high, the gated…
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What is a valid-ready slice staller? How does a staller work?
In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below: In the regular case, “stall_en” is low, and the staller…
