Chipress

Floorplan is required for topographical synthesis / production synthesis, as well as physical design. It often requires designer feedback due to the following reasons.

Synthesis Re-spin Time

There are quite a few factors impacting synthesis re-spin time, such as timing closure difficulty, logic levels, logic complexity, etc. Two most important factors are standard cell area and standard cell instance count.

We found a strong positive correlation between synthesis runtime and standard cell area & instance count. This makes sense, as synthesis essentially maps RTL to gate-level netlist.

Designers may have to partition a large design or system into multiple sub-designs or sub-systems based on functionality along with the desired standard cell area and instance count. The physical design team then provides floorplans for each sub-design or sub-system, which will be synthesized in different parallel runs.

In each synthesis run, we typically limit the total standard cell area to be around 100K um2, and limit total standard cell count to be around 2 million, resulting in a runtime between 2 and 4 days.

Area Saving

The floorplan should not be too large for area saving. In each sub-design or sub-system, other than standard cell area and instance count, designers should also provide macro (such as SRAM) area and instance count. By having the overall area number, the physical design can provide a reasonably sized floorplan.

Timing Closure

On the other hand, the floorplan should not be too small. This would cause utilization being too high, and in turn, poor timing. A small floorplan could limit the synthesis tool’s timing optimization capability, for example, when a violating setup timing path could be fixed by standard cell upsizing. Ideally, after topographical synthesis / production synthesis, the utilization rate should fall between 60% and 70%.

In addition, designers should provide information, such as data flow directions and interactions across different blocks to the physical design team. This information will guide the physical design team which blocks should be placed together. For example, if a wide memory is implemented using 2 narrow banks, the 2 banks should be placed together. Another example, a memory controller’s data reordering logic (standard cells) should be placed close to data storage (SRAM or some other hard macro). If two tightly coupled blocks are placed far away in the chip, the STA team may face huge amounts of time violations and spend unnecessary effort on timing fixes.

Routing and Wiring Resource Saving

Proper design or system partitioning based on designers’ feedback saves routing and wiring resources in upper metal layers, and majority of the routing can be done in lower metal layers.