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Understand Cache Coherence from Memory Model’s Perspective
To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to coherence shared memory systems. In the world of computer architecture,…
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DFT (VIII) – How does DFT test SRAMs? What is the Memory Built-In Selft Test (MBIST)?
SRAM Fault Model Similar to the logic fault model, SRAMs can have stuck-at faults and open faults in memory cells. In addition, SRAMs can have other faults, including: Memory cell transition fault, i.e., failure to undergo either 0 -> 1 or 1 -> 0 transition Memory cell coupling fault, i.e., transition in one cell value…
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What is auto-ungrouping? How does it impact the implementation flow?
Besides boundary optimization, auto-ungroup is another important synthesis optimization technique. By flattening design hierarchies for the benefit of PPA, it enables cross boundary optimization, and removes logic duplication, which often occurs for shared signals across replicated modules. Auto-ungrouping will introduce hierarchy naming changes. For example, ungrouped hierarchies will use underscore “_” instead of slash “/”…
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Two recommended readings for learning UPF
Unified Power Format (UPF), is a set of Tcl-like commands used to define the low-power design intent for SoCs. Using UPF commands, you will be able to specify supply networks, power switches, isolation, retention, and other aspects relevant to power management of a chip design. One of the recommended readings for learning UPF, is “Synopsys…
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How to get better PPA for Synthesis?
We discussed how RTL coding can help with PPA. In this post, we share a few guidelines detailing how to get better PPA during synthesis. Category Guideline Description Synthesis Friendly RTL Coding Style Do not handcrafting arithmetic operations such as multiplications by shifting and adding. This prevents synthesis tools from identifying them as arithmetic operations,…
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From CPU ISA to CPU Microcode Hacking
The Google security team identified EntrySign, an AMD Zen-based CPU security vulnerability issue. This is a perfect opportunity to understand various CPU instruction concepts, including ISA, CISC, microcode, and microcode patching. What is ISA? An Instruction Set Architecture (ISA) defines the fundamental instruction set a CPU understands, and it creates a boundary between CPU hardware…
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How Andrej Karpathy uses LLMs
Andrej Karpathy, a former research scientist and a founding member of OpenAI, had a great video showing how he uses LLMs in his own life. We highly recommend everyone to watch this video, and try taking advantage of LLMs in daily life. The following are what we find from the video particularly useful for hardware…
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How to avoid cache interference in SoC DRAM testing?
In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data. Avoid Cache Interference in Software Based Testing To avoid cache interference completely, testing software should explicitly initiate a cache flush…
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How to do SoC DRAM Testing?
SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study. Test 0 – Address Walking Ones Test Walking Ones means, only 1 bit of…
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What are SoC DRAM faults?
DRAM related faults can be roughly classified into: Stuck-At Fault (SAF): the DRAM cell is stuck at 0 or 1 Transitional Fault (TF): the DRAM cell value cannot be flipped if a write operation intends to flip it Coupling Fault (CF): a DRAM cell value can change when writing to a different DRAM cell Neighborhood…
