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A Recommended Reading: “Metal ECO implementation using Mask Programmable cells”
Metal ECO is vital to absorb late design changes before tapeout. It could save millions of dollars in mask cost. Traditionally, metal ECO takes advantage of spare functional cells sprinkled across the design during the physical design phase. However, traditional metal ECO has inherent limitations:…
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What should you ask the interviewer at the end of an interview?
An interview runs in two ways: while the interviewer is testing you and evaluating your potential, you should also assess if the team is suitable for you. You should typically expect a question from your interviewer at the end of each interview: “any questions for…
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Leverage “Behavioral Interview for Software Engineers” for Hardware Interviews
In hardware interviews, it is not uncommon to cover behavioral questions. In fact, quite a few companies, such as Amazon, Intel and Apple, specifically have behavioral interviews. To succeed in hardware interviews, candidates should master both technical and behavioral questions. Although no specific books exist…
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What to Do If Setup Time and Hold Time Have Conflicts?
It is not uncommon to see setup time and hold time conflicting in STA. It could be caused by: Some timing paths may only face one factor, while the other paths may see multiple factors. Timing paths with setup time and hold time conflicting can…
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How to Deal with Noise / Crosstalk in Physical Design?
In our book “Crack the Hardware Interview – Physical Design & Silicon Debug”, we discussed that noise fix is an essential step during timing ECOs. We will dive a little deeper into this topic. What is Noise / Crosstalk? Noise / crosstalk analysis is a…
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What is DVFS? What is AVFS?
DVFS stands for Dynamic Voltage Frequency Scaling, and it is a common dynamic power reduction technique used in IC design. It achieves minimal power consumption by adjusting voltage and frequency based on the performance and power requirements of different chip workloads. To implement DVFS, an…
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Multi-Bit Cell for Low Power Design
Multi-bit cells have widely been used in low power design, and various EDA tools offer extensive support for multi-bit cells in chip design. As the name suggests, a multi-bit cell merges multiple logic bits in the same cell. For example, 4 flop bits can be…
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FV Interview Questions (XIV) – What If SEC Cannot Achieve Full Proof?
It is not always possible to achieve full proof in the SEC, but there are still a few things we can try for better SEC convergence. We discussed a few techniques for FPV convergence, including design reduction, black boxing, and abstraction. They can all be…
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FV Interview Questions (XIII) – What is SEC and How Does It Work?
In our book “Crack the Hardware Interview: Verification, Implementation, Synthesis and Power”, we discussed Formal Equivalence Verification (FEV). The goal of FEV is to check if two designs, Specification Model (SPEC design) and Implementation Model (IMP design), are equivalent. There are 2 major applications of…
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Jim Keller’s View Towards “HW / SW Contract” in AI Chips
In DAC61, Jim presented his view towards “HW / SW Contract” in AI chips. It is definitely worth watching his keynote in DAC61. In the CPU world, the ISA + programming & execution model is obviously the contract between HW and SW engineers. However, unlike…
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