chipressian
-
Will Overclocking the Design Speed Up the DV Simulation?
Some engineers may think, increasing clock frequency, or overclocking the design can speed up DV simulation. This would be wrong. Modern simulation tools are discrete-event based. They model the operation of the design as a sequence of events in time. Each event occurs at a…
-
Unpacked Arrays in SystemVerilog Testbench
There are 4 types of unpacked arrays commonly used in SystemVerilog testbench: The following shows how to instantiate these unpacked arrays The table below shows a comparison across all array types above, especially in terms of performance: Type Memory Index Application & Performance Fixed Size…
-
How to implement hardware for a 3-number sorter?
If sorting of 3 numbers must complete in 1 cycle, then the optimal solution is to use 3 comparators. The diagram below shows the implementation: This design can easily be pipelined, if timing becomes an issue. If it is not required to get the array…
-
A Recommended Reading: “Metal ECO implementation using Mask Programmable cells”
Metal ECO is vital to absorb late design changes before tapeout. It could save millions of dollars in mask cost. Traditionally, metal ECO takes advantage of spare functional cells sprinkled across the design during the physical design phase. However, traditional metal ECO has inherent limitations:…
-
What should you ask the interviewer at the end of an interview?
An interview runs in two ways: while the interviewer is testing you and evaluating your potential, you should also assess if the team is suitable for you. You should typically expect a question from your interviewer at the end of each interview: “any questions for…
-
Leverage “Behavioral Interview for Software Engineers” for Hardware Interviews
In hardware interviews, it is not uncommon to cover behavioral questions. In fact, quite a few companies, such as Amazon, Intel and Apple, specifically have behavioral interviews. To succeed in hardware interviews, candidates should master both technical and behavioral questions. Although no specific books exist…
-
What to Do If Setup Time and Hold Time Have Conflicts?
It is not uncommon to see setup time and hold time conflicting in STA. It could be caused by: Some timing paths may only face one factor, while the other paths may see multiple factors. Timing paths with setup time and hold time conflicting can…
-
How to Deal with Noise / Crosstalk in Physical Design?
In our book “Crack the Hardware Interview – Physical Design & Silicon Debug”, we discussed that noise fix is an essential step during timing ECOs. We will dive a little deeper into this topic. What is Noise / Crosstalk? Noise / crosstalk analysis is a…
-
What is DVFS? What is AVFS?
DVFS stands for Dynamic Voltage Frequency Scaling, and it is a common dynamic power reduction technique used in IC design. It achieves minimal power consumption by adjusting voltage and frequency based on the performance and power requirements of different chip workloads. To implement DVFS, an…
-
Multi-Bit Cell for Low Power Design
Multi-bit cells have widely been used in low power design, and various EDA tools offer extensive support for multi-bit cells in chip design. As the name suggests, a multi-bit cell merges multiple logic bits in the same cell. For example, 4 flop bits can be…
Read Our Books for Free with Kindle Unlimited
Our books are available on Kindle Unlimited for free. Plus, you get unlimited access to hundreds of other books for preparing hardware interviews, including our recommended reading list
* Chipress participates in the Amazon Services LLC Associates Program, an affiliate advertising program designed to provide a means for sites to earn advertising fees by advertising and linking to Amazon.com
Subscribe
Enter your email to get updates from us. You might need to check the spam folder for the confirmation email.
Chipress 