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How to Eliminate Metastability Caused by Reset Removal?
In practice, reset assertion is asynchronous and de-assertion is synchronous. Synchronous reset de-assertion can make sure flops are under metastability after reset removal. However, due to place and route, reset de-assertion does not happen simultaneously for all flops in an SoC. RTL designers must be…
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How to Boost Emulation Performance & Efficiency?
Emulation is commonly used in hardware verification and validation. Unlike simulation where all RTL / hardware activities are modeled in software domain, emulation is running on both software and hardware. The table below shows a comparison between RTL / hardware simulation and emulation: Simulation Emulation…
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How does Synthesis Tool do Boundary Optimization?
Boundary Optimization is a synthesis optimization technique to exploit functional constraints across design hierarchies. Boundary Optimization includes the following: The diagram below shows each of the above techniques. Note, optimizations within the sub-design are not considered as Boundary Optimizations, for example, constant and unloaded register…
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Design a DDR Memory Controller (V) – Timing Parameters
Before the memory control issues a command to DDR devices, it checks if certain timing parameters are met, otherwise the DDR device cannot work properly. There are tons of timing parameters in JEDEC standards, and each DDR generation / device type could have different timing…
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How to Verify SRAMs are Integrated Properly?
SRAMs are widely used in SOC design. To verify SRAMs are integrated into the design properly, design engineers should write SVAs wherever SRAMs are used, or embed SVAs in SRAM wrappers. These SVAs will eventually be used in DV simulation and FV. In functional mode,…
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What If an RTL Bug is Found after RTL Freeze?
It is not uncommon to find RTL bugs after RTL freeze. Typically after RTL freeze, DV and FV team will continue running regressions, and a corner-case RTL bug might be uncovered at this point. The first step would be figuring out the exact reproducing recipe,…
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Learning Embedded Systems from YouTubers
Unlike a general-purpose computer, embedded systems are often specialized and customized for a dedicated function. Embedded systems are everywhere. They can be found in automotive systems, home appliances, GPS navigators, fitness trackers, consumer electronics, etc. Luckily, there are tons of open-source or free online materials…
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How to do Inter-Thread Communications (ITC) in SystemVerilog Testbench?
In SystemVerilog testbench, concurrent threads require communication to establish control of sequence of execution. There are 3 types of inter-thread communications (ITC): Event-based ITC Synchronized operation of concurrent threads is achieved via event variables: a thread waits for an event to be triggered, and an…
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How to Achieve Concurrency in SystemVerilog Testbench?
SystemVerilog testbench components run concurrently, and concurrent components run as separate threads. The threads are spawned, coordinated, and synchronized. They typically share the state information of a process, and share memory and other resources directly. A DV simulator can only execute one thread at a…
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How to Enforce SystemVerilog Constrant Solver Order?
Inside a constraint block, there is NO implied order of how the variable values will be solved. The SystemVerilog constraint solver is free to choose the variables to randomize first. Let us look at an example below. The intention is to randomize “addrType” first, and…
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