Physical Design
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What to Do If Setup Time and Hold Time Have Conflicts?
It is not uncommon to see setup time and hold time conflicting in STA. It could be caused by: Some timing paths may only face one factor, while the other paths may see multiple factors. Timing paths with setup time and hold time conflicting can…
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How to Deal with Noise / Crosstalk in Physical Design?
In our book “Crack the Hardware Interview – Physical Design & Silicon Debug”, we discussed that noise fix is an essential step during timing ECOs. We will dive a little deeper into this topic. What is Noise / Crosstalk? Noise / crosstalk analysis is a…
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What is DVFS? What is AVFS?
DVFS stands for Dynamic Voltage Frequency Scaling, and it is a common dynamic power reduction technique used in IC design. It achieves minimal power consumption by adjusting voltage and frequency based on the performance and power requirements of different chip workloads. To implement DVFS, an…
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Multi-Bit Cell for Low Power Design
Multi-bit cells have widely been used in low power design, and various EDA tools offer extensive support for multi-bit cells in chip design. As the name suggests, a multi-bit cell merges multiple logic bits in the same cell. For example, 4 flop bits can be…
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