chipressian
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Learning UVM: 2 Free Online Resources
UVM (Universal Verification Methodology) is the most popular verification framework used in the ASIC / SOC industry. Unfortunately, there are not a whole lot of resources for people to study UVM themselves, and many schools do not teach UVM in classrooms. We found 2 free…
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RTL Implementation of Integer Division by Constants
In our 1st book in “Crack the Hardware Interview”, we discussed how to implement arbitrary integer division in RTL, and such division takes several clock cycles to complete and is costly in physical implementation. It is also quite common to implement integer division by constant…
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Transistor Evolution: from Planar to FinFET to NanoSheet
Conventional transistors come with a 2D planar structure, where both source and drain are implemented beneath the surface of the silicon substrate. However, as the process advances, it gets harder and harder to achieve high frequency response, high channel control, and low leakage currents. Starting…
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LFSR (Linear Feedback Shift Register): Randomize in Digital World
In digital design, we quite often need to generate random numbers. However, it is impossible to achieve true randomness in the digital world. Therefore, design engineers use LFSR (Linear Feedback Shift Register) to generate pseudo-random sequences. Why Randomness is Needed in Digital Design? Randomness is…
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3 EDA Playgrounds: Free Online RTL Simulators & Waveform Editor
Traditional commercial EDA tools usually cost tens of thousands annually, and it introduces high bars for people who want to enter the hardware industry. Unlike the software industry, there are not a whole lot of open-source hardware tools for people to try out freely. Luckily,…
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Signal Manipulation in RTL: Edge Detection, Pulse & Level Signal Conversions
How to detect signal edges, as well as how to convert between pulse and level signals, are frequently asked in ASIC / RTL design interviews. We intend to cover these RTL signal manipulation techniques in this post. Rising Edge Detection RTL implementation of rising edge…
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Design a DDR Memory Controller (IV) – RAS & Power Saving Control
The DDR memory controller should typically be equipped with RAS features and saving control. We will cover these two topics in this post. RAS Features RAS stands for Reliability, Availability, and Serviceability. If there exists data corruption, either internal to the DDR memory controller or…
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Design a DDR Memory Controller (III) – Arbitration, Scheduling & QoS
We discussed how a DDR memory controller deals with data hazards in previous posts. Let us look at how the DDR memory controller handles DDR command arbitration, scheduling and QoS. There are many ways to implement DDR command arbitration and scheduling, and we show one…
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Design a DDR Memory Controller (II) – Data Hazards Handling
We provided an overview of a DDR memory controller architecture in previous posts. One important aspect that impacts the controller architecture, is data hazards handling. Note, the data hazards we discuss here is from AXI master’s perspective. Write After Write (WAW) hazards can happen, when…
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Design a DDR Memory Controller (I) – An Overview
We will cover DDR memory controller design in this post. Note, there are many ways to implement DDR memory controllers, and we show one possible implementation as a case study. As shown below, on one side, a DDR memory controller takes read and write requests…
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