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Design a DDR Memory Controller (II) – Data Hazards Handling
We provided an overview of a DDR memory controller architecture in previous posts. One important aspect that impacts the controller architecture, is data hazards handling. Note, the data hazards we discuss here is from AXI master’s perspective. Write After Write (WAW) hazards can happen, when a DDR write packet resides in the Write Command Pool,…
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Design a DDR Memory Controller (I) – An Overview
We will cover DDR memory controller design in this post. Note, there are many ways to implement DDR memory controllers, and we show one possible implementation as a case study. As shown below, on one side, a DDR memory controller takes read and write requests from system fabric. The source of these requests can be…
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RTL Implementations of 3 Must Know Encoding Techniques
There are quite a few encoding techniques used in modern ASIC design. In this post, we will cover RTL implementations of 3 must know encoding techniques. Binary / 1-Hot Encoding To implement binary to 1-hot encoding, using 3-bit binary number for example: It is a good practice to write an SVA, making sure “oneHot” is…
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2 Version Control Tools in ASIC Design Industry: Git & Perforce
Version control tools are critical for large projects such as ASIC / SOC developments and they enable cross functional team collaborations. The version control tools maintain a record of every change complete with authorship, timestamp, and many other details. ASIC / SOC engineers must be proficient in check-in / check-out / branch / merge commands…
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Design a sync FIFO using single-port SRAMs
In our 1st book in series “Crack the Hardware Interview”, we discussed how to design a sync FIFO using a dual-port SRAM. Assuming the same size of storage, single-port SRAMs typically come with a smaller area than dual-port SRAMs. Therefore, using single-port SRAMs as sync FIFO storage is a more common practice and a more…
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How to implement hardware for array sorting in ascending order (III) – Using Linear Algebra?
In a previous post, we discussed one possible array sort solution without comparators. There are more comparison-free array sorting implementations available. In paper “An Efficient O(N) Comparison-Free Sorting Algorithm”, Saleh Abel-Hafeez and Ann Gordon-Ross proposed a new sorting algorithm, targeted for custom, IC-designed applications, such as GPU, and video processing DSP chips. The idea is…
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How to implement hardware for array sorting in ascending order (II) – Without Comparator?
In a previous post, we discussed hardware implementation for array sorting using comparators. However, it is also possible to sort arrays without comparators. Surajeet Ghosh, Shaon Dasgupta and Sanchita Saha Ray presented a novel solution in their paper “A Comparison-Free Hardware Sorting Engine”. We will cover the high-level idea and a few implementation details of…
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How to implement hardware for array sorting in ascending order (I) – With Comparator?
Implementing hardware based array sorting is frequently asked when interviewing with high frequency trading companies. There are quite a few software based sorting algorithms that hardware implementation can leverage. If interested, you can go to this site and get a visual idea how each sorting algorithm works with random initial order. In the following discussions,…
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How to “evaluate” the hiring manager during an interview?
Since the hiring manager has a direct impact on your future career growth in the company, it is important for you to evaluate whether you would like to work with the hiring manager in the future. The most effective approach is to get the opinions / feedback from other people’s mouths if they have worked…
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Design a DDR Memory Controller (VI) – DRAM hierarchy & DDR Address Decoding
A typical DRAM hierarchy looks like this: It is possible that a particular DRAM product does not include one or more hierarchies listed above. For example, DIMM was commonly seen in desktops and servers, not in smart phones or watches; Bank Group (BG) was introduced in DDR4; Channel (CH) was introduced in LPDDR4, etc. Due…
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