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Best RTL Coding Practice for Better PPA
Many times, different RTL coding styles in the same piece of code result in different PPA (Power, Performance, Area). Let us dive into a few examples. Use Register Enable Conditions When coding data pipelines, it is a good practice to always explicitly include an enable condition, as the synthesis tool could infer clock gaters for…
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Chip Harvesting – Definition, Benefits and Design Considerations
What is Chip Harvesting? Chip harvesting is a common technique to reduce cost and increase overall yield, by salvaging defective parts of logic or memory. Defective part of the chip will be fuse-isolated from the working parts, and the chip can still be shipped to market and delivered to consumers. This technique has long been…
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DFT (VII) – What is Boundary Scan?
The system board is mounted with fully-tested scannable ASIC SoCs, and scan-based ASIC testing is used to detect defects inside these SoCs. However, these internal scan chains are not useful to detect board-level faulty traces. To detect faults on the system board, the concept of boundary scan and its associated industry standard JTAG (Joint Action…
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DFT (VI) – Rules & Some Design Guidelines
We briefly discussed the concept of scan-based ASIC testing, and there are certain rules associated with DFT, such that the SoC can achieve a good coverage. We will cover a few DFT design guidelines in this post. All Clocks Must Be Controllable by DFT Modes This is done using a bypass mux in ATPG mode.…
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DFT (V) – What is Internal Scan / Scan-Based ASIC Testing?
ATPG uses a method called internal scan, or scan-based ASIC testing to test sequential logic in the design. We will discuss scan-based ASIC testing in this post. Internal scan methodology replaces the regular flops with scan flops. Compared to regular flops, scan flops have two extra inputs, SI (Scan Input) and SE (Scan Enable), and…
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DFT (IV) – What is Logic Build-In Self Test (LBIST)?
All ASIC testing methodology we discussed so far requires Automatic Test Equipment (ATE). There is a different class of ASIC testing method, called Logic Built-In Self Test (LBIST), whose test pattern data is largely moved off the external ATE, and onto the silicon die itself. The basic LBIST architecture is shown below: LBIST uses LFSR…
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DFT (III) – What is ATPG?
The following diagram shows a typical Automated Test Equipment (ATE) architecture: The test program / test pattern is stored in pattern memory, and ATE applies the stimulus per predefined test patterns. ATE then measures DUT response and matches it with the expected response. The test patterns are generated by tools, not by functional tests, hence…
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DFT (II) – What is Fault Model?
ASIC / SOC testability is important during chip fabrication, and fault model is used to represent the effects of a physical defect. There are quite a few types of fault models, among which the most common ones are stuck-at fault, bridging fault, and open fault: To learn more, we recommend interviewees to study Chapter 3…
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DFT (I) – Why is ASIC / SOC Testability Important?
During chip pre-silicon verification, RTL and DV engineers work together to check the functionality of the HDL model of a chip. Engineers utilize simulation, or formal verification, to make sure an SoC is well designed and logically free of errors. However, silicon may still fail due to physical defects arising from fabrication. Such defects include…
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Software API of Hardware Accelerators: A Quick Overview
Modern SoC equips with varieties of hardware accelerators for different types of workloads, for example: The heart of an SoC is the CPU, and it is where the Operating System (OS) is running. A driver is the software that tells the OS how to communicate with a hardware accelerator in the SoC, and the OS…
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