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Handling non-atomic operations in snooping based MSI protocol (I)
In cache coherence protocol implementation, designers must properly handle non-atomic operations, since coherence transactions cannot complete instantly. We start from the well-known snooping based MSI protocol base model (without considering atomicity), and discuss atomicity handling in real world. Base Model Given the following assumptions: The…
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How to avoid unintended fixed priority arbiter usage in RTL?
We discussed how to optimize PPA in RTL coding, and we will cover how to avoid unintended fixed priority arbiters in RTL. Fixed priority arbiters are “expensive” in RTL implementation. The more requests the arbiter has, the more level of logic the final grant will…
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Understanding Power Analysis & Estimation: 2 Recommended Readings
As SoCs are getting more complex, power becomes just as important as functionality correctness or performance. This article, “Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff” by Infineon Technologies, addresses the growing challenges in accurately estimating and correlating power in complex SoCs.…
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What we learnt from Gemini Prompting Guide 101
Google released its “Gemini Prompting Guide 101” a while ago. Though the majority of the examples in this guide use Google Workspace for illustration purposes, it still provides a general ideal of writing effective prompts for all LLMs. The guide Four first illustrates the 4…
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Understand Cache Coherence from Memory Model’s Perspective
To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to…
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DFT (VIII) – How does DFT test SRAMs? What is the Memory Built-In Selft Test (MBIST)?
SRAM Fault Model Similar to the logic fault model, SRAMs can have stuck-at faults and open faults in memory cells. In addition, SRAMs can have other faults, including: Note, SRAM read and write logic, such as sense amplifiers and I/O buffers can have defects, but…
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What is auto-ungrouping? How does it impact the implementation flow?
Besides boundary optimization, auto-ungroup is another important synthesis optimization technique. By flattening design hierarchies for the benefit of PPA, it enables cross boundary optimization, and removes logic duplication, which often occurs for shared signals across replicated modules. Auto-ungrouping will introduce hierarchy naming changes. For example,…
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Two recommended readings for learning UPF
Unified Power Format (UPF), is a set of Tcl-like commands used to define the low-power design intent for SoCs. Using UPF commands, you will be able to specify supply networks, power switches, isolation, retention, and other aspects relevant to power management of a chip design.…
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How to get better PPA for Synthesis?
We discussed how RTL coding can help with PPA. In this post, we share a few guidelines detailing how to get better PPA during synthesis. Category Guideline Description Synthesis Friendly RTL Coding Style Do not handcrafting arithmetic operations such as multiplications by shifting and adding.…
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From CPU ISA to CPU Microcode Hacking
The Google security team identified EntrySign, an AMD Zen-based CPU security vulnerability issue. This is a perfect opportunity to understand various CPU instruction concepts, including ISA, CISC, microcode, and microcode patching. What is ISA? An Instruction Set Architecture (ISA) defines the fundamental instruction set a…
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