DRAM
-
How to avoid cache interference in SoC DRAM testing?
In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data. Avoid Cache Interference in Software Based Testing To avoid cache…
-
How to do SoC DRAM Testing?
SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study. Test 0 – Address…
-
What are SoC DRAM faults?
DRAM related faults can be roughly classified into: Before an SoC is shipped to customers, its DRAM has to go through extensive DRAM testing, e.g., MemTest86. This makes sure that the refresh operation is sufficient to prevent data loss, and that the DRAM bus does…
-
Design a DDR Memory Controller (V) – Timing Parameters
Before the memory control issues a command to DDR devices, it checks if certain timing parameters are met, otherwise the DDR device cannot work properly. There are tons of timing parameters in JEDEC standards, and each DDR generation / device type could have different timing…
-
Design a DDR Memory Controller (IV) – RAS & Power Saving Control
The DDR memory controller should typically be equipped with RAS features and saving control. We will cover these two topics in this post. RAS Features RAS stands for Reliability, Availability, and Serviceability. If there exists data corruption, either internal to the DDR memory controller or…
-
Design a DDR Memory Controller (III) – Arbitration, Scheduling & QoS
We discussed how a DDR memory controller deals with data hazards in previous posts. Let us look at how the DDR memory controller handles DDR command arbitration, scheduling and QoS. There are many ways to implement DDR command arbitration and scheduling, and we show one…
-
Design a DDR Memory Controller (II) – Data Hazards Handling
We provided an overview of a DDR memory controller architecture in previous posts. One important aspect that impacts the controller architecture, is data hazards handling. Note, the data hazards we discuss here is from AXI master’s perspective. Write After Write (WAW) hazards can happen, when…
-
Design a DDR Memory Controller (I) – An Overview
We will cover DDR memory controller design in this post. Note, there are many ways to implement DDR memory controllers, and we show one possible implementation as a case study. As shown below, on one side, a DDR memory controller takes read and write requests…
-
Design a DDR Memory Controller (VI) – DRAM hierarchy & DDR Address Decoding
A typical DRAM hierarchy looks like this: It is possible that a particular DRAM product does not include one or more hierarchies listed above. For example, DIMM was commonly seen in desktops and servers, not in smart phones or watches; Bank Group (BG) was introduced…
Read Our Books for Free with Kindle Unlimited
Our books are available on Kindle Unlimited for free. Plus, you get unlimited access to hundreds of other books for preparing hardware interviews, including our recommended reading list
* Chipress participates in the Amazon Services LLC Associates Program, an affiliate advertising program designed to provide a means for sites to earn advertising fees by advertising and linking to Amazon.com
Subscribe
Enter your email to get updates from us. You might need to check the spam folder for the confirmation email.
Chipress 