books
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Published: The 2nd Edition of Our Book Series “Crack the Hardware Interview”
We are thrilled to announce that, the second edition of “Crack the Hardware Interview” is released! We published the first edition of this book series in early 2024, and received quite a few positive feedback. The second edition is still structured in the same way…
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Leverage “Behavioral Interview for Software Engineers” for Hardware Interviews
In hardware interviews, it is not uncommon to cover behavioral questions. In fact, quite a few companies, such as Amazon, Intel and Apple, specifically have behavioral interviews. To succeed in hardware interviews, candidates should master both technical and behavioral questions. Although no specific books exist…
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DFT (VII) – What is Boundary Scan?
The system board is mounted with fully-tested scannable ASIC SoCs, and scan-based ASIC testing is used to detect defects inside these SoCs. However, these internal scan chains are not useful to detect board-level faulty traces. To detect faults on the system board, the concept of…
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DFT (V) – What is Internal Scan / Scan-Based ASIC Testing?
ATPG uses a method called internal scan, or scan-based ASIC testing to test sequential logic in the design. We will discuss scan-based ASIC testing in this post. Internal scan methodology replaces the regular flops with scan flops. Compared to regular flops, scan flops have two…
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DFT (IV) – What is Logic Build-In Self Test (LBIST)?
All ASIC testing methodology we discussed so far requires Automatic Test Equipment (ATE). There is a different class of ASIC testing method, called Logic Built-In Self Test (LBIST), whose test pattern data is largely moved off the external ATE, and onto the silicon die itself.…
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DFT (III) – What is ATPG?
The following diagram shows a typical Automated Test Equipment (ATE) architecture: The test program / test pattern is stored in pattern memory, and ATE applies the stimulus per predefined test patterns. ATE then measures DUT response and matches it with the expected response. The test…
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DFT (II) – What is Fault Model?
ASIC / SOC testability is important during chip fabrication, and fault model is used to represent the effects of a physical defect. There are quite a few types of fault models, among which the most common ones are stuck-at fault, bridging fault, and open fault:…
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DFT (I) – Why is ASIC / SOC Testability Important?
During chip pre-silicon verification, RTL and DV engineers work together to check the functionality of the HDL model of a chip. Engineers utilize simulation, or formal verification, to make sure an SoC is well designed and logically free of errors. However, silicon may still fail…
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Design a DDR Memory Controller (VI) – DRAM hierarchy & DDR Address Decoding
A typical DRAM hierarchy looks like this: It is possible that a particular DRAM product does not include one or more hierarchies listed above. For example, DIMM was commonly seen in desktops and servers, not in smart phones or watches; Bank Group (BG) was introduced…
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How to quickly learn scripting languages for ASIC design interviews?
In ASIC design and implementation flows, Tcl and Python are the 2 most widely used scripting languages: Therefore, it is important to master these 2 scripting languages for ASIC design interview preparation. We recommend the following 2 books if you want to learn Tcl and…
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