News & Trends
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The Bridge Builders: A Guide to Landing the Product Development Engineer Role in Semiconductors
The modern world runs on silicon. Every advanced device, from your phone’s processor to the chip in a self-driving car, relies on flawless, high-volume manufacturing. This is where the Product Development Engineer (PDE) steps in. They’re the critical bridge. They are the ultimate product owner.…
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What we learnt from Gemini Prompting Guide 101
Google released its “Gemini Prompting Guide 101” a while ago. Though the majority of the examples in this guide use Google Workspace for illustration purposes, it still provides a general ideal of writing effective prompts for all LLMs. The guide Four first illustrates the 4…
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From CPU ISA to CPU Microcode Hacking
The Google security team identified EntrySign, an AMD Zen-based CPU security vulnerability issue. This is a perfect opportunity to understand various CPU instruction concepts, including ISA, CISC, microcode, and microcode patching. What is ISA? An Instruction Set Architecture (ISA) defines the fundamental instruction set a…
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How Andrej Karpathy uses LLMs
Andrej Karpathy, a former research scientist and a founding member of OpenAI, had a great video showing how he uses LLMs in his own life. We highly recommend everyone to watch this video, and try taking advantage of LLMs in daily life. The following are…
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Published: The 2nd Edition of Our Book Series “Crack the Hardware Interview”
We are thrilled to announce that, the second edition of “Crack the Hardware Interview” is released! We published the first edition of this book series in early 2024, and received quite a few positive feedback. The second edition is still structured in the same way…
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Jim Keller’s View Towards “HW / SW Contract” in AI Chips
In DAC61, Jim presented his view towards “HW / SW Contract” in AI chips. It is definitely worth watching his keynote in DAC61. In the CPU world, the ISA + programming & execution model is obviously the contract between HW and SW engineers. However, unlike…
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Chipress’ Social Profile is Up!
As an effort to enhance our online presence, we set up our social profile in various social media platforms. Follow us on LinkedIn, X, Instagram, Threads, and Facebook, to get instant updates from us. For everyone’s convenience, we aggregated all our social profile in LinkTree,…
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Transistor Evolution: from Planar to FinFET to NanoSheet
Conventional transistors come with a 2D planar structure, where both source and drain are implemented beneath the surface of the silicon substrate. However, as the process advances, it gets harder and harder to achieve high frequency response, high channel control, and low leakage currents. Starting…
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A Must Read List of Papers for ASIC Design Interviews
Yet Another Latch and Gotchas Paper by Don Mills This paper discusses several SystemVerilog coding topics that can lead to inadvertent design bugs, including casex / casez expressions and unique / priority case statements. It is a recommended reading before using these SystemVerilog new features.…
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