Verification
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How to improve re-build time during test case development?
During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are…
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Semiconductor ATE Testing: Why Every Chip Needs a Test
I. The Imperative of Testing: Quality, Cost, and Reliability Semiconductor testing is a non-negotiable step in modern manufacturing, driven by quality, reliability, and cost control. The key tool is the Automatic Test Equipment (ATE), a sophisticated, computer-controlled machine that runs software to apply electrical signals…
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The Bridge Builders: A Guide to Landing the Product Development Engineer Role in Semiconductors
The modern world runs on silicon. Every advanced device, from your phone’s processor to the chip in a self-driving car, relies on flawless, high-volume manufacturing. This is where the Product Development Engineer (PDE) steps in. They’re the critical bridge. They are the ultimate product owner.…
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How to resolve SVA false failure with gated clocks?
In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: “config_regs” can legally be changed when “block_busy” is low, during which the gated clock does not toggle and the SVA does not check its consequent…
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What is a valid-ready slice staller? How does a staller work?
In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below:…
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How to avoid cache interference in SoC DRAM testing?
In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data. Avoid Cache Interference in Software Based Testing To avoid cache…
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How to do SoC DRAM Testing?
SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study. Test 0 – Address…
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What are SoC DRAM faults?
DRAM related faults can be roughly classified into: Before an SoC is shipped to customers, its DRAM has to go through extensive DRAM testing, e.g., MemTest86. This makes sure that the refresh operation is sufficient to prevent data loss, and that the DRAM bus does…
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SEC Mapping Types: Cutpoint Mapping vs Stopat Mapping
We discussed how SEC works using clock gating FV in a previous post, and introduced cutpoint mapping. We will extend the discussion about the SEC mapping types in this post. A cutpoint is a pair of internal signals that you expect to be equal. The…
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How to Boost Emulation Performance & Efficiency?
Emulation is commonly used in hardware verification and validation. Unlike simulation where all RTL / hardware activities are modeled in software domain, emulation is running on both software and hardware. The table below shows a comparison between RTL / hardware simulation and emulation: Simulation Emulation…
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