Interview Questions
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FV Interview Questions (IV) – Dealing with Complexity by Design Reduction
In our book “Crack the Hardware Interview: Verification, Implementation, Synthesis & Power”, we briefly discussed what to do if FV cannot achieve full proof. Design reduction is an important technique to tackle this problem. We will dive a little deeper in post. Many designs have…
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FV Interview Questions (III) – How to Waive an Expected Failing Property?
Typically we want to get full proof for all assert properties and see all cover properties proven reachable. However, sometimes we may want to disable certain properties from being run during FV. For example, the FV VIP supports all features of a protocol, but the…
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FV Interview Questions (II) – How to Do FSM Checks?
Jasper Gold offers “fsm_checks” command to auto-generate properties for FSM state / transition reachability. When running this command, the tool automatically detects FSM state variables or accepts user-specified FSM state variables, and extracts cover properties to prove. To define a conceptual FSM from the the…
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FV Interview Questions (I) – How to Debug Unreachable Properties?
During formal verification, sometimes we may see unreachable properties. Using Cadence Jasper Gold for example, it can be flagged as either unreachable cover properties, or passing yet never triggered assert properties. This can be caused by over constraints, i.e., excessive assume properties, or design bugs.…
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Why Should We Never Use Self-Determined Expressions in RTL?
A self-determined expression is the one whose bit length is solely determined by the expression itself. SystemVerilog LRM defines the bit lengths resulting from self-determined expressions. In the table below, i, j, and k represent expressions of an operand, while L(i) represents the operand i’s…
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Hash Function and Its Applications: Hash CAM & Bloom Filter
A hash function defines the mapping relationship of (key, value) pairs. Good hash functions should be very fast to compute (easy for hardware implementation), and should minimize duplication of output values (less collisions). How to Implement a Hash Function? One common approach to implement a…
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SCCB(Ⅲ) — Protocol Structure
We covered SCCB protocol signaling in previous post, and we will dive into the SCCB structure in this post. Below is the diagram of SCCB, it shows one master device connects to one slave device. Multiple slave devices can be connected to the same bus.…
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Best Practice for Defining Configuration Registers
In the ASIC design industry, there are certain configuration register definition guidelines that RTL designers should follow. This is to achieve the following purposes: Allowing software / firmware / verification teams to migrate code to new projects faster Improving maintainability and scalability of software /…
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Best Practice for RTL Naming Conventions
In this post, we share a few RTL naming conventions for better readability. See the table below. RTL Naming Convention RTL Naming Convention Use intelligible signal / variable names Better readability is achieved if the RTL code is “self-documented” Use “<name>_clk” for the name of…
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SCCB (Ⅱ) — Protocol Signaling
After an overview of the SCCB protocol, we will dive into SCCB signaling in details. Below is the Pin description from the specification: SCCB_ESCCB_E is an active-low, one-directional signal controlled by the master device. During data transmission, SCCB_E must be set to 0; When bus…
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