Interview Questions
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Understand Cache Coherence from Memory Model’s Perspective
To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to…
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DFT (VIII) – How does DFT test SRAMs? What is the Memory Built-In Selft Test (MBIST)?
SRAM Fault Model Similar to the logic fault model, SRAMs can have stuck-at faults and open faults in memory cells. In addition, SRAMs can have other faults, including: Note, SRAM read and write logic, such as sense amplifiers and I/O buffers can have defects, but…
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What is auto-ungrouping? How does it impact the implementation flow?
Besides boundary optimization, auto-ungroup is another important synthesis optimization technique. By flattening design hierarchies for the benefit of PPA, it enables cross boundary optimization, and removes logic duplication, which often occurs for shared signals across replicated modules. Auto-ungrouping will introduce hierarchy naming changes. For example,…
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Two recommended readings for learning UPF
Unified Power Format (UPF), is a set of Tcl-like commands used to define the low-power design intent for SoCs. Using UPF commands, you will be able to specify supply networks, power switches, isolation, retention, and other aspects relevant to power management of a chip design.…
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How to get better PPA for Synthesis?
We discussed how RTL coding can help with PPA. In this post, we share a few guidelines detailing how to get better PPA during synthesis. Category Guideline Description Synthesis Friendly RTL Coding Style Do not handcrafting arithmetic operations such as multiplications by shifting and adding.…
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From CPU ISA to CPU Microcode Hacking
The Google security team identified EntrySign, an AMD Zen-based CPU security vulnerability issue. This is a perfect opportunity to understand various CPU instruction concepts, including ISA, CISC, microcode, and microcode patching. What is ISA? An Instruction Set Architecture (ISA) defines the fundamental instruction set a…
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How to avoid cache interference in SoC DRAM testing?
In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data. Avoid Cache Interference in Software Based Testing To avoid cache…
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How to do SoC DRAM Testing?
SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study. Test 0 – Address…
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What are SoC DRAM faults?
DRAM related faults can be roughly classified into: Before an SoC is shipped to customers, its DRAM has to go through extensive DRAM testing, e.g., MemTest86. This makes sure that the refresh operation is sufficient to prevent data loss, and that the DRAM bus does…
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SEC Mapping Types: Cutpoint Mapping vs Stopat Mapping
We discussed how SEC works using clock gating FV in a previous post, and introduced cutpoint mapping. We will extend the discussion about the SEC mapping types in this post. A cutpoint is a pair of internal signals that you expect to be equal. The…
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