Implementation Flows
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What are LEC abort points? How to debug aborts?
It is not uncommon to see abort points during LEC. They are the key points that have not been proven either equivalent or non-equivalent based on the current tool settings, such as compare effort or compare algorithms. There are several possible causes of abort points:…
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Understanding Power Analysis & Estimation: 2 Recommended Readings
As SoCs are getting more complex, power becomes just as important as functionality correctness or performance. This article, “Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff” by Infineon Technologies, addresses the growing challenges in accurately estimating and correlating power in complex SoCs.…
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DFT (VIII) – How does DFT test SRAMs? What is the Memory Built-In Selft Test (MBIST)?
SRAM Fault Model Similar to the logic fault model, SRAMs can have stuck-at faults and open faults in memory cells. In addition, SRAMs can have other faults, including: Note, SRAM read and write logic, such as sense amplifiers and I/O buffers can have defects, but…
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What is auto-ungrouping? How does it impact the implementation flow?
Besides boundary optimization, auto-ungroup is another important synthesis optimization technique. By flattening design hierarchies for the benefit of PPA, it enables cross boundary optimization, and removes logic duplication, which often occurs for shared signals across replicated modules. Auto-ungrouping will introduce hierarchy naming changes. For example,…
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Two recommended readings for learning UPF
Unified Power Format (UPF), is a set of Tcl-like commands used to define the low-power design intent for SoCs. Using UPF commands, you will be able to specify supply networks, power switches, isolation, retention, and other aspects relevant to power management of a chip design.…
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How to get better PPA for Synthesis?
We discussed how RTL coding can help with PPA. In this post, we share a few guidelines detailing how to get better PPA during synthesis. Category Guideline Description Synthesis Friendly RTL Coding Style Do not handcrafting arithmetic operations such as multiplications by shifting and adding.…
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How can latch arrays save power? How do they work?
In the digital design world, data storages in magnitude of MegaBytes (MB), KiloBytes (KB) and Bytes (B), are typically implemented using DRAM, SRAM and flops, respectively. Flop arrays, in particular, can sometimes be replaced with latch arrays, to optimize power. An Idea and A Concept…
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How to Eliminate Metastability Caused by Reset Removal?
In practice, reset assertion is asynchronous and de-assertion is synchronous. Synchronous reset de-assertion can make sure flops are under metastability after reset removal. However, due to place and route, reset de-assertion does not happen simultaneously for all flops in an SoC. RTL designers must be…
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How does Synthesis Tool do Boundary Optimization?
Boundary Optimization is a synthesis optimization technique to exploit functional constraints across design hierarchies. Boundary Optimization includes the following: The diagram below shows each of the above techniques. Note, optimizations within the sub-design are not considered as Boundary Optimizations, for example, constant and unloaded register…
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Why Should We Never Use Self-Determined Expressions in RTL?
A self-determined expression is the one whose bit length is solely determined by the expression itself. SystemVerilog LRM defines the bit lengths resulting from self-determined expressions. In the table below, i, j, and k represent expressions of an operand, while L(i) represents the operand i’s…
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