Architecture
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SCCB(Ⅲ) — Protocol Structure
We covered SCCB protocol signaling in previous post, and we will dive into the SCCB structure in this post. Below is the diagram of SCCB, it shows one master device connects to one slave device. Multiple slave devices can be connected to the same bus.…
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Best Practice for Defining Configuration Registers
In the ASIC design industry, there are certain configuration register definition guidelines that RTL designers should follow. This is to achieve the following purposes: Guidelines for Configuration Register Content Guidelines for Configuration Register Address Map
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SCCB (Ⅱ) — Protocol Signaling
After an overview of the SCCB protocol, we will dive into SCCB signaling in details. Below is the Pin description from the specification: Below waveform would help you to have a better understanding of the signal behavior during SCCB protocol data transmission.
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SCCB (I) — A Protocol in Image Sensor
Serial Camera Control Bus (SCCB) is defined and deployed by OmniVision Technologies, Inc. Most of the functions in OmniVision image sensors can be controlled by SCCB. The image sensor will be used as a slave device, and one master device will connect to at least…
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Software API of Hardware Accelerators: A Quick Overview
Modern SoC equips with varieties of hardware accelerators for different types of workloads, for example: The heart of an SoC is the CPU, and it is where the Operating System (OS) is running. A driver is the software that tells the OS how to communicate…
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Design a DDR Memory Controller (IV) – RAS & Power Saving Control
The DDR memory controller should typically be equipped with RAS features and saving control. We will cover these two topics in this post. RAS Features RAS stands for Reliability, Availability, and Serviceability. If there exists data corruption, either internal to the DDR memory controller or…
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Design a DDR Memory Controller (III) – Arbitration, Scheduling & QoS
We discussed how a DDR memory controller deals with data hazards in previous posts. Let us look at how the DDR memory controller handles DDR command arbitration, scheduling and QoS. There are many ways to implement DDR command arbitration and scheduling, and we show one…
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Design a DDR Memory Controller (II) – Data Hazards Handling
We provided an overview of a DDR memory controller architecture in previous posts. One important aspect that impacts the controller architecture, is data hazards handling. Note, the data hazards we discuss here is from AXI master’s perspective. Write After Write (WAW) hazards can happen, when…
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Design a DDR Memory Controller (I) – An Overview
We will cover DDR memory controller design in this post. Note, there are many ways to implement DDR memory controllers, and we show one possible implementation as a case study. As shown below, on one side, a DDR memory controller takes read and write requests…
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Design a DDR Memory Controller (VI) – DRAM hierarchy & DDR Address Decoding
A typical DRAM hierarchy looks like this: It is possible that a particular DRAM product does not include one or more hierarchies listed above. For example, DIMM was commonly seen in desktops and servers, not in smart phones or watches; Bank Group (BG) was introduced…
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