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What are LEC abort points? How to debug aborts?
It is not uncommon to see abort points during LEC. They are the key points that have not been proven either equivalent or non-equivalent based on the current tool settings, such as compare effort or compare algorithms. There are several possible causes of abort points:…
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How to improve re-build time during test case development?
During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are…
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How to resolve SVA false failure with gated clocks?
In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: “config_regs” can legally be changed when “block_busy” is low, during which the gated clock does not toggle and the SVA does not check its consequent…
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What is a valid-ready slice staller? How does a staller work?
In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below:…
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How to optimize coherence conflict / false sharing?
Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line.…
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How to handle coherent DMA?
A coherent DMA operation that reads memory should get the most recent version of data, even if the data resides in a cache in state M or O. Similarly, a coherent DMA operation that writes memory must invalidate stale copies in all caches. Though it…
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What are the advantages and disadvantages of using write-through cache in cache coherence protocol?
We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Advantages of using write-through caches: Disadvantage of using write-through cache: Reference A Primer on Memory Consistency and Cache Coherence (Second Edition), by Vijay Nagarajan, Daniel J. Sorin,…
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Handling non-atomic requests in directory based MSI protocol (II)
In the previous post, we discussed about handling non-atomic requests in directory based MSI protocol by stalls. In cache controller transient states such as “IS-D”, “IM-A” and “SM-A”, we could allow forwarded request messages to make progress without stalling, at the expense of adding more…
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Handling non-atomic requests in directory based MSI protocol (I)
Just like snooping based protocols, directory based cache coherence protocol has to handle non-atomic requests in real world implementations. We start from the a directory based MSI base model, and discuss one solution on non-atomic requests handling. Base Model In directory based MSI protocol, there…
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Handling non-atomic operations in snooping based MSI protocol (II)
In the previous post, we discussed non-zero delay from coherence requests to responses. However, coherence requests may also be non-atomic: a coherence request may not be instantly ordered when it is issued by a cache controller. For example, if there is a request queue between…
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