Verification
-
How to write efficient DV constraints?
Split Bigger Problem into Smaller Ones Instead of mixing everything together, splitting bigger problems into smaller steps offers better performance. One may consider using “Solve-Before” for user defined solving order. In addition, it is also recommended to sequence constraint solving in “pre_randomize()” and “post_randomize()” whenever…
-
What can cause a simulation hang?
Simulation hang is a condition where simulator functionalities cannot advance. We can only observe that nothing meaningful has happened for a long time. Simulation hang can be caused by RTL bugs, testbench (TB) issues, or C-model errors. RTL Bugs A combinational loop in RTL can…
-
How to improve re-build time during test case development?
During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are…
-
Semiconductor ATE Testing: Why Every Chip Needs a Test
I. The Imperative of Testing: Quality, Cost, and Reliability Semiconductor testing is a non-negotiable step in modern manufacturing, driven by quality, reliability, and cost control. The key tool is the Automatic Test Equipment (ATE), a sophisticated, computer-controlled machine that runs software to apply electrical signals…
-
The Bridge Builders: A Guide to Landing the Product Development Engineer Role in Semiconductors
The modern world runs on silicon. Every advanced device, from your phone’s processor to the chip in a self-driving car, relies on flawless, high-volume manufacturing. This is where the Product Development Engineer (PDE) steps in. They’re the critical bridge. They are the ultimate product owner.…
-
How to resolve SVA false failure with gated clocks?
In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: “config_regs” can legally be changed when “block_busy” is low, during which the gated clock does not toggle and the SVA does not check its consequent…
-
What is a valid-ready slice staller? How does a staller work?
In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below:…
-
How to avoid cache interference in SoC DRAM testing?
In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data. Avoid Cache Interference in Software Based Testing To avoid cache…
-
How to do SoC DRAM Testing?
SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study. Test 0 – Address…
-
What are SoC DRAM faults?
DRAM related faults can be roughly classified into: Before an SoC is shipped to customers, its DRAM has to go through extensive DRAM testing, e.g., MemTest86. This makes sure that the refresh operation is sufficient to prevent data loss, and that the DRAM bus does…
Read Our Books for Free with Kindle Unlimited
Our books are available on Kindle Unlimited for free. Plus, you get unlimited access to hundreds of other books for preparing hardware interviews, including our recommended reading list
* Chipress participates in the Amazon Services LLC Associates Program, an affiliate advertising program designed to provide a means for sites to earn advertising fees by advertising and linking to Amazon.com
Subscribe
Enter your email to get updates from us. You might need to check the spam folder for the confirmation email.
Chipress 