Chipress

Yet Another Latch and Gotchas Paper by Don Mills

This paper discusses several SystemVerilog coding topics that can lead to inadvertent design bugs, including casex / casez expressions and unique / priority case statements. 

It is a recommended reading before using these SystemVerilog new features.

Simulation and Synthesis Techniques for Asynchronous FIFO Design by Clifford E. Cummings

Async FIFOs are commonly used to pass data from one clock domain to another asynchronous clock domain. This paper details one async FIFO implementation using Gray code pointers. 

This is a must read paper during your ASIC design interview preparation, as async FIFO is widely used in modern SoC design, and it is one of the most popular interview topics.

Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog by Clifford E. Cummings

This paper presents quite a few CDC strategies, and it covers safely passing both one bit and multiple bits of signals across CDC boundaries. In addition, the paper shows detailed RTL implementations of these CDC techniques, which is quite valuable.

Synchronization and Metastability by Steve Golson

This paper explains how Mean Time Between Failures (MTBF) are calculated and design considerations of CDC synchronization.

No Man’s Land, Constraining Async Clock Domain Crossings by Paul Zimmer

This paper illustrates one key hidden assumption of async FIFO Gray code pointers, which is often overlooked by design engineers. It also proposed a few techniques for how to properly constrain these pointers in real practice.

Highly Efficient LRU Implementations for High Associativity Cache Memory by J.P. Grossman

LRU replacement policy is the optimal solution for cache design when reducing miss rate is required. This paper provides detailed analysis for various LRU implementations, including Square Matrix, Counter, Linked List, Systolic Array, etc.

Overall, it is a comprehensive review of LRU implementations, and it will definitely help ASIC design interview preparation.

A Review of Clock Gating Techniques by Jagrit Kathuria, M. Ayoubkhan, Arti Noor

This paper presents a review of gate-level implementations for various clock gating cells. The latch based clock gating cells are definitely must read for ASIC design interviews.