Chipress

Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line.

The coherence traffic incurred by coherence conflict / false sharing hurts performance when a core is waiting for coherence permissions for data access, and increases the load on the interconnection network / fabric.

The possibility of false sharing is a function of the cache line size; a larger cache line can hold more unrelated pieces of data, thus a larger cache line is more prone to false sharing.

Without reducing the cache line size, coherence can be enforced at a finer granularity. However, this requires extra state bits for each line.

Speculation can help to reduce false sharing as well. If the predictors determine a line is invalid due to false sharing, the core can speculatively use the data in the line until it obtains the coherence permission to the line. If the prediction is correct, it overcomes the performance penalty of false sharing, but it does not save the load on the interconnection network / fabric.

Reference

A Primer on Memory Consistency and Cache Coherence (Second Edition), by Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood