Chipress

DRAM related faults can be roughly classified into:

1. Stuck-At Fault (SAF): the DRAM cell is stuck at 0 or 1
2. Transitional Fault (TF): the DRAM cell value cannot be flipped if a write operation intends to flip it
3. Coupling Fault (CF): a DRAM cell value can change when writing to a different DRAM cell
4. Neighborhood Pattern Sensitive Fault (NPSF): a specific type of fault triggered only by specific patterns of data written to or read from neighboring DRAM cells, rather than always manifested in a given location
5. Address Fault (AF): a fault related to DRAM address decoding
6. Peripheral Fault (PF): a fault related to DRAM peripheral circuitries, such as sense amplifier and precharge logic

Before an SoC is shipped to customers, its DRAM has to go through extensive DRAM testing, e.g., MemTest86. This makes sure that the refresh operation is sufficient to prevent data loss, and that the DRAM bus does not corrupt addresses and data in transit.

Many SoCs embed with RAS features like ECC, greatly increasing resiliency against DRAM spontaneous corruption. These RAS features are commonly seen in server systems and data centers. For many consumer products, however, the DRAM data is not protected, relying solely on a well-designed memory refresh.