Chipress

DVFS stands for Dynamic Voltage Frequency Scaling, and it is a common dynamic power reduction technique used in IC design. It achieves minimal power consumption by adjusting voltage and frequency based on the performance and power requirements of different chip workloads.

To implement DVFS, an EMU or Energy Management Unit is required. EMU generates different voltages to supply part or all of the logic circuits, effectively reducing overall power consumption while still meeting frequency requirements.

During the chip physical design process, STA engineers must close timing on multiple corners and in multiple modes, or so-called multi-mode multi-corner STA. Particularly, STA engineers must sign-off timing on all possible corners in each operation mode, introducing extra timing sign-off complexity and effort.

It is important to note that DVFS adjusts voltage and frequency using a fixed set of values. AVFS (Adaptive Voltage Frequency Scaling), on the contrary, can adjust voltage and frequency in a much finer granularity.

AVFS significantly increases the timing sign-off complexity and effort, since:

1. It is challenging to cover all combinations of voltage and frequency with a few PVT (Process, Voltage, Temperature) conditions
2. Adding more PVT conditions leads to too many sign-off corners
3. When timing library is incomplete, designers may need to create custom libraries

Therefore, in practice, AVFS is less widely used, and DVFS are more commonly seen in chip design.