Chipress

As SoCs are getting more complex, power becomes just as important as functionality correctness or performance.

This article, “Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff” by Infineon Technologies, addresses the growing challenges in accurately estimating and correlating power in complex SoCs.

This article is a good start to understand how the ASIC industry handles power concerns intelligently and early. If you are interested in power analysis and estimation flows, it is definitely worth reading the paper, or at least going over the slides.

Separately, glitch power is often overlooked by RTL designers during power estimation, yet it accounts for a large portion of dynamic power wastes. A proper glitch power modeling methodology is necessary for better correlations between pre-silicon power estimation and post-silicon power analysis.

This patent, “Method for Modeling Glitch of Logic Gates” by MediaTek engineers, introduces a novel method, called “Glitch Scaler”, to accurately model glitches in simulation. After reading this patent, you should get a better understanding of the cause of glitch power, as well as how modern EDA tools model glitches in simulation.

References:

1. https://www.design-reuse.com/article/60948-unified-methodology-for-effective-correlation-of-soc-power-estimation-and-signoff/
2. https://www.slideshare.net/slideshow/unified-methodology-for-effective-correlation-of-soc-power/190657561
3. https://patents.google.com/patent/US10810337B2