Chipress

SRAM Fault Model

Similar to the logic fault model, SRAMs can have stuck-at faults and open faults in memory cells.

In addition, SRAMs can have other faults, including:

1. Memory cell transition fault, i.e., failure to undergo either 0 -> 1 or 1 -> 0 transition
2. Memory cell coupling fault, i.e., transition in one cell value flips another victim cell
3. Address decoder open fault, e.g., address decoder selects two words instead of one
4. Address decoder bridging fault, e.g., address decode selects both words, or one word is inaccessible

Note, SRAM read and write logic, such as sense amplifiers and I/O buffers can have defects, but their faults are equivalent to memory cell faults.

How does DFT Test SRAMs?

DFT relies on a functional testing approach, rather than a structural approach, to test SRAMs.

For example, Memory-Scan (MSCAN) Algorithm does the following sequence:

1. From 0 to MAX_ADDR, write 0s to each address
2. From 0 to MAX_ADDR, read each address and make sure read data is 0
3. From 0 to MAX_ADDR, write 1s to each address
4. From 0 to MAX_ADDR, read each address and make sure read data is 1

It is obvious that MSCAN Algorithm is quite effective in detecting memory cell stuck-at faults. However, it does not detect either memory cell 1 -> 0 transition fault, or memory cell coupling fault. Thus MSCAN Algorithm is a minimal test.

DFT often requires more thorough and more comprehensive functional memory test algorithms for robustness, such as March C- Algorithm:

1. From 0 to MAX_ADDR, write 0s to all addresses
2. From 0 to MAX_ADDR, read each address, make sure read data is 0, and write 1s back to the same address
3. From 0 to MAX_ADDR, read each address, make sure read data is 1, and write 0s back to the same address
4. From MAX_ADDR to 0, read each address, make sure read data is 0, and write 1s back to the same address
5. From MAX_ADDR to 0, read each address, make sure read data is 1, and write 0s back to the same address
6. From 0 to MAX_ADDR, read each address, and make sure read data is 0

At the end of March C- Algorithm, it makes sure:

1. A total of 10 read or write operations are performed at each address
2. All memory cells have been at 0 and 1 upon completion
3. All memory cells have undergone a 0 -> 1 and a 1 -> 0 transition
4. Any stuck-at fault, transition fault, or coupling fault is detected

Note, SRAM tests always require linear test time, which is proportional to the SRAM address range.

What is MBIST?

Unlike logic testing, SRAM testing relies more on Built-In Self Testing (MBIST) rather than ATPG. Therefore, MBIST bypasses the low-bandwidth ATE connection and reduces ATE pattern memory size.

Similar to LBIST, a Memory BIST controller generates the required test patterns and implements the SRAM test algorithms, and a comparator to check the read data from SRAM.

The MBIST controller and the comparator are typically synthesized with the functional RTL, to meet the target clock rate. Thus MBIST can save lots of test application time.

Depending on the chip size, one or more MBIST controllers are instantiated in the design, controlling all SRAMs in the chip. The comparators may be shared by multiple SRAMs. The more SRAMs share the same comparator, the less parallelism we have, thus the longer the SRAM testing takes.