How to get better PPA for Synthesis?

We discussed how RTL coding can help with PPA. In this post, we share a few guidelines detailing how to get better PPA during synthesis.

Category	Guideline Description
Synthesis Friendly RTL Coding Style	Do not handcrafting arithmetic operations such as multiplications by shifting and adding. This prevents synthesis tools from identifying them as arithmetic operations, and the tools will not be able to use better architectures to implement the arithmetic operations. Allow synthesis tools to infer adders, subtractors, and multipliers.
Synthesis Friendly RTL Coding Style	Do not do manual shift-and-add for constant multiplications. Let the synthesis tools infer a multiplier even for constant multiplications.
Synthesis Friendly RTL Coding Style	Use signed operators for any design that needs signed arithmetic. Avoid mixing unsigned and signed data types in the same expression. Avoid manual sign extension. Declare appropriate signal types for the synthesis tools to handle sign extensions automatically.
Synthesis Friendly RTL Coding Style	Do not manually negate operands since it prevents Sum-of-Product (SoP) extraction and it has a negative impact on QoS. Simply put a “-” sign before a negative value, to get its absolute value.
Synthesis Friendly RTL Coding Style	Combining adders / multipliers / absolute operations. Add / Multiply / Absolute operations separated by other operands, such as clipping / shifting, could lead to multiple instantiations of adders / multipliers in synthesis. Move other operands like clipping / shifting around, to allow synthesis tools to combine adders / multipliers to reduce timing pressure and save power.
Synthesis Friendly RTL Coding Style	Keeping relevant operations in the same design hierarchy, allows synthesis tools to perform more logic optimizations. For example, within the same design hierarchy, synthesis tools look at the design at the operator level and identify clusters of arithmetic operations that can be potentially merged. Instead of implementing multiple discrete arithmetic operations, synthesis tools can merge them as one large complex operation. Arithmetic operations merging can happen for: 1. Vector Sum: x + y + z 2. Multiply and Add: x * y + z 3. Sum of Product: w * x + y * z, etc.
Synthesis Tool Settings	Enable Auto-ungroup. Auto-ungroup removes logic duplication, which often occurs for shared signals across replicated modules
Synthesis Tool Settings	Enable boundary optimizations
Synthesis Tool Settings	Enable register replication to help timing
Synthesis Tool Settings	Enable retiming. Synthesis tools can move combinational logic across pipeline stages for better timing, without human intervention
Synthesis Tool Settings	Use Booth Encoding multipliers. Booth encode the less active operand to reduce the signal toggling in multiplication