Chipress

In SoC DRAM testing, the existence of a cache could interfere with the testing accuracy. This is because, when initiating a DRAM access from the CPU, a cache instead of DRAM could supply the data.

Avoid Cache Interference in Software Based Testing

To avoid cache interference completely, testing software should explicitly initiate a cache flush when switching from one test mode to the other. This would make sure DRAMs are always accessed in the new test mode.

If the cache hint is configurable, then testing software could also explicitly set all DRAM accesses as non-cacheable. Alternatively, if the cache itself can be disabled, then testing software could disable cache completely in DRAM testing.

Separately, if the test address range is larger than cache size, then write from high address to low address, and then read from low address to high address.

There are some other tricks in decreasing possibilities of cache hit during DRAM testing. For example, use out-of-order accesses or non-uniformed address patterns.

Avoid Cache Interference in Hardware Based Testing

Most SoC DRAM testing methodology involves writing / reading data with certain patterns to / from certain addresses. Essentially, DRAM testing can be implemented in hardware, i.e., a FSM with configurable data patterns and address sequences.

This piece of test hardware should support various types of address sequences, generate required data patterns, automate the data checking and report test completion / test errors. It should be able to communicate with DDR PHY directly, bypassing cache and any possible address remapping / reordering introduced by the DRAM controller.

Another subtle advantage for hardware based testing is, it bypasses any instruction reordering introduced by CPU instruction pipelining. Software based testing has to be initiated from CPU, while hardware based testing does not involve CPU at all.

One example is Intel’s Converged Pattern Generator and Checker (CPGC), providing standardized DRAM training and testing capability. Compared to software based testing, CPGC significantly improves testing efficiency and accuracy.

Intel introduced Advanced Memory Test (AMT) features by integrating CPGC into its server Memory Reference Code (MRC). By default, AMT and CPGC are disabled, as they will significantly increase the system boot time. But they can be enabled through the BIOS setup utility. See Intel’s technical paper below for more details.

Reference:
https://www.intel.com/content/dam/support/us/en/documents/server-products/memory-replacement-guideline-and-amt-guide-for-dsg-server-systems.pdf