How to do SoC DRAM Testing?

SoC DRAM testing can be done either in hardware or software. We focus on software methods here. PassMark’s MemTest86 is probably the most popular SoC DRAM testing software, especially for consumer products. We use MemTest86 test kit for our case study.

Test 0 – Address Walking Ones Test

Walking Ones means, only 1 bit of the address bits can be 1, and all other address bits are 0. The “1” will be shifted to a different address bit in each iteration.

In one iteration, a value is written to an address P1 and a different value is written to a different address P2. Both P1 and P2 satisfy the Walking Ones pattern. The test then initiates a read to address P1, and checks if the read data is correct.

This test is used to detect Address Fault (AF), for example, possible short / open circuit issues in address lines, and SoC / DRAM controller address decoding errors.

Test 1 & 2 – Own Address Tests

In these tests, each DRAM address is written with its own address and is checked for data consistency. They are effective in detecting data integrity issues in each DRAM cell, as well as address decoding issues in memory subsystems.

Test 3, 4, 5 & 7 – Moving Inversions Tests

Moving Inversion tests will first fill data with certain patterns in DRAM, and then invert values for each address from low to high after checking DRAM data values. If no errors are found, it subsequently inverts values for each address from high to low after checking DRAM data values, essentially restoring the original data pattern. The aforementioned iteration could be performed multiple passes in the same test, to improve the effectiveness.

These tests have the same advantage as Test 0, 1 & 2. On top of that, it detects Coupling Fault (CF) or Neighborhood Pattern Sensitive Fault (NPSF), and DRAM refreshing issues via multi-pass testing. Note, these tests allow enabling caches.

Test 6 – Block Move Test

This test moves large trunks of data across different regions in DRAM address space, and identifies possible errors occurred during data movements.

It is quite useful in detecting memory subsystem stability issues under high workload, cache coherency issues, and DRAM bus signal integrity issues.

Test 8, 11 & 12 – Random Number Sequence

As its name suggests, these tests write random numbers and subsequently check read data values. However, unlike moving inversion tests, the test writing and checking are only done in forward direction, i.e., from low to high address.

Test 9 – Modulo-N Test

This test writes a certain pattern into addresses Px that satisfy [(Addr % N) == 0], and writes a different pattern into all other addresses Py. It then reads from addresses Px, and verifies the read data is correct.

Modulo-N tests are quite effective in detecting Coupling Fault (CF) or Neighborhood Pattern Sensitive Fault (NPSF), and uncovering errors that are not detected by moving inversions due to cache.

Test 10 – Bit Fade Test

This test detects if DRAM can retain the write data. A failing test indicates possible insufficient DRAM refreshing issues. This can be caused by incorrect DRAM controller settings, unstable supply voltage, or defective DRAM cells.

Test 13 – Row Hammer Test

The increased densities of DRAM cells could result in lower operational noise margins. The repeated opening / closing of DRAM rows may cause charge leakage in adjacent rows, and even cause bits to flip.

This test “hammers” rows by alternatively reading two addresses in a repeated pattern, and then verifies the contents of DRAM cells remain the same.

One possible solution to mitigate the Row Hammer Effect, is to increase the DRAM refresh frequency. However, this is less desired since it introduces higher power consumption and increased processing overhead.

Starting from LPDDR4, JEDEC standard includes optional hardware support for the so-called Target Row Refresh (TRR). Internally, TRR identifies possible victim rows, and refreshes these rows to prevent bit flips.

Test 14 – DMA Test

All previous tests are initiated by the CPU. What makes this test stand out is, it is initiated by DMA without CPU intervention. It is designed to detect memory errors exposed during DMA-based memory accesses initiated by peripheral devices.

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