Chipress

In the digital design world, data storages in magnitude of MegaBytes (MB), KiloBytes (KB) and Bytes (B), are typically implemented using DRAM, SRAM and flops, respectively. Flop arrays, in particular, can sometimes be replaced with latch arrays, to optimize power.

An Idea and A Concept

Conceptually, a posedge triggered flop consists of a low-transparent latch and a high-transparent latch:

1. When clock transitions from low to high, the low-transparent latch “locks” the data, and data is then propagated through the high-transparent latch
2. When clock transitions from high to low, the high-transparent latch “locks” the data and keep the data output stable, while the low-transparent latch “prepares” the data for next cycle

One may wonder, is it possible to reduce 2 latches per bit storage to 1 latch per bit? This is where the latch array comes into play:

The potential area reduction introduced by latch arrays helps to reduce static power / leakage power. In addition, clock pin capacitance is reduced due to a smaller number of transistors, which in turn reduces dynamic power.

How do Latch Arrays Work?

The diagram below shows one possible latch array circuitry, where all latches are clock low-transparent.

As soon as write enable “we” asserts, the incoming write data “wdata” and write address “waddr” are stored in flops; in the following cycle, write data “wdata_q” is latched into the latch array, and it is available for read. Note, for the latch array, both “locking” write data and “supplying” read data require half-cycle timing closure. The half-cycle timing path could lead to potential timing closure challenges.

Conclusion

Compared with a regular flop array, the latch array equips with some extra peripheral logic to work properly, such as clock gater and write data & address flops. Obviously, the latch array does not always bring area and power improvements.

If the array depth is shallow, it might not be worth replacing flop arrays with latch arrays. RTL engineers should carefully analyze the design and make trade-offs appropriately.