Chipress

Before the memory control issues a command to DDR devices, it checks if certain timing parameters are met, otherwise the DDR device cannot work properly.

There are tons of timing parameters in JEDEC standards, and each DDR generation / device type could have different timing requirements. Fortunately, from DDR controller’s perspective, only 4 major categories are commonly assessed / used:

1. Activate command timing
2. Precharge command timing
3. Read and Write command timing
4. Refresh command timing

Activate command

Activate command shall be issued before any Read or Write command can be executed. It “opens” a row of a bank, by “copying” an entire row to a row buffer, for future read or write accesses.

Parameter Name	Meaning
tRRD	The minimum time interval between Activate commands to different banks
tRC	The minimum time interval between Active commands to the same bank
tFAW	In a rolling tFAW window, no more than 4 banks may be activated

Precharge command

Precharge command, on the contrary, “closes” a bank. If a bank is open, it stores the row buffer content back to the DRAM array. Precharge command must be issued, if the DRAM controller wants to read or write a different bank row.

Parameter Name	Meaning
tRAS	Row active time, the minimum time interval from Activate command to Precharge command for the same bank.
tRP	Row precharge time, the minimum time interval from Precharge command to Activate command for the same bank. Some devices may differentiate per-bank Precharge time and all-bank Precharge time using “tRPpb” and “tRPab”, respectively
tPPD	Precharge to Precharge delay

Read and Write commands

Read and Write commands timing are primarily defined with respect to Activate and Precharge commands, and to themselves.

Parameter Name	Meaning
tRCD	The minimum time interval between Activate commands and Read/Write commands. Sometimes it is also called RAS-to-CAS delay
tCCD	CAS-to-CAS delay. DDR devices often support burst Read and Write operations. DDR Data bus can only serve data transfer for one Read / Write command at a time, thus consecutive Read and Write commands must be sufficiently apart, to eliminate “data collision”
tRTP	Read-to-Precharge delay. From Read command presents on DDR Command Bus, to read data presents on DDR Data Bus, there is a Read Latency (RL). Due to Read Latency (RL), a bank must remain “open” until the entire read data burst complets.
tRTW	Read-to-Write delay. Before Read Latency (RL) expires and the read data burst completes, the DDR Data Bus cannot transfer write data. Note that, from Write command presents on DDR Command Bus, to write data presents on DDR Data Bus, there is also a Write Latency (WL), tRTW can often be represented as (RL + read_data_burst_length – WL + some_margin). It is obvious that, due to tRTW, a Read command and a Write command cannot be back-to-back, thus read-to-write switch shall be minimized for data bus utilization.
tWR	Write recovery time. After a burst write operation, tWR must be met before a Precharge command to the same bank can be issued
tWTR	Write-to-Read delay. It is often equal to (WL + write_data_burst_length + tWR). It is obvious that, due to tWTR, a Write command and a Read command cannot be back-to-back, thus write-to-read switch shall be minimized for data bus utilization.

Refresh command

DDR devices store data using capacitors. Without periodically refreshing, current leakage will eventually lead to data loss. Refresh commands are critical on DDR data retention.

Note, a bank must be “closed” before it can be “refreshed”.

Similar to the Precharge command, certain DDR devices differentiate per-bank Refresh time (with “pb” suffix) and all-bank Refresh time (with “ab” suffix).

Parameter Name	Meaning
tFAW	In a rolling tFAW window, no more than 4 banks may be refreshed, when doing per-bank Refresh. All-bank Refresh does not have such requirements
tRFCpb / tRFCab	Minimum time interval between the Refresh command and the next valid command (e.g., Activate command and Refresh command)
tRPpb / tRPab	Row precharge time, the minimum time interval between bank “closure” and Refresh command
tREFI	A bank must be refreshed regularly, in every tREFI interval. tREFI requirements vary on device types, operating temperature, etc.

Disclaimer

This post intends to provide an overview of DDR timing parameters. Refer to JEDEC standards for more details.

DDR devices typically offer various low power modes, which we do not cover in this post. In addition, before a DDR device can access read and write access, it has to go through a certain training process, and there are certain timing requirements specifically for training.