Chipress

SRAMs are widely used in SOC design. To verify SRAMs are integrated into the design properly, design engineers should write SVAs wherever SRAMs are used, or embed SVAs in SRAM wrappers. These SVAs will eventually be used in DV simulation and FV.

In functional mode, these SVAs may include:

1. Read and write to the same address shall never happen in the same cycle. In single-port SRAMs, this is obviously not allowed. Dual-port SRAMs of certain types can support concurrent read and write accesses, but not all. If a dual-port SRAM support this feature, one should add a cover property
2. Read and write addresses shall never exceed the SRAM ranges. This is particularly important for SRAMs with non-power-of-2 entries
3. After enabling the SRAM read data cache, the read data shall still match the write data (If the SRAM read pattern is repetitive, one can instantiate a small piece of cache at the output of the SRAM. Read data to the same address can be supplied by the cache, instead of from the SRAM array. Suppressing “redundant” read accesses to SRAM could save a significant amount of dynamic power, however, the presence of the cache introduces verification challenges. One can also consider using Sequential Equivalence Check or SEC, to verify the SRAM behaves the same with and without the cache instantiation)

In low-power mode, these SVAs may include:

1. SRAM read and write shall never happen in low-power mode
2. In low-power mode, the clock and the power control signals must satisfy certain timing requirements (We have an extensive discussion in our book “Crack the Hardware Interview – Verification, Implementation, Synthesis & Power”)

Typically, the SRAM models from the fab do not embed low-power related SVAs intrinsically. If low-power protocol is violated, the SRAM models will simply provide 0 read data for all read access onwards.

Adding these low-power related SVAs would be optional, but it would be beneficial for debugging and locating the earliest failing point more efficiently.