Chipress

Some engineers may think, increasing clock frequency, or overclocking the design can speed up DV simulation. This would be wrong.

Modern simulation tools are discrete-event based. They model the operation of the design as a sequence of events in time. Each event occurs at a particular timestamp and marks a change of design states. Between consecutive events, design states remain unchanged and the simulation time can directly jump to the occurrence of the next event.

Overclocking the design in DV simulation does not impact the sequences and changes of design state, thus it does not help with simulation speed. Sometimes it even hurts DV simulations and raises false alarms whenever timing requirements are specified with absolute time values.

DDR timing parameters are one good example, and DDR memory controllers can only count cycles to control DDR command timing. Since DDR memory controllers work under a certain frequency, designers will configure the DDR timing counters with fixed values. When a DDR memory controller is overclocked in DV simulation, DDR memory VIP could error out with timing requirements violated, but these are false errors.

Another example would be SRAM power down and power up timing. These timing requirements are specified in absolute time as well.

It is worth pointing out that, in emulation or hardware based simulation, overclocking does help with test speed.

References:

1. https://en.wikipedia.org/wiki/Discrete-event_simulation