Chipress

Multi-bit cells have widely been used in low power design, and various EDA tools offer extensive support for multi-bit cells in chip design.

As the name suggests, a multi-bit cell merges multiple logic bits in the same cell. For example, 4 flop bits can be implemented using four 1-bit DFFs, or two 2-bit multi-bit DFF cells, or one 4-bit multi-bit DFF cell.

Multi-bit merging is not as simple as placing multiple standard cells together. Instead, it involves integration and optimization at transistor level. Assuming a 1-bit DFF takes 0.25 um², then a 2-bit multi-bit DFF cell would generally be smaller than 0.5 um², and a 4-bit multi-bit DFF cell would be much smaller than 1 um².

In terms of power reduction, multi-bit cells have a few advantages over single-bit cells:

1. Single-bit cells and multi-bit cells have no significant difference on clock pin capacitance. When a large number of single-bit DFFs in the design are replaced with multi-bit DFFs, the overall clock pin capacitance on the clock tree will be reduced a lot, in turn, so does the overall clock switching power
2. Due the same reason above, after using multi-bit cells, the same clock tree buffer can drive more bits, thus fewer numbers of buffers and less buffer area needed for clock tree design, and less clock switching power and clock tree leakage power

However, improper placement of multi-bit cells may lead to routing congestion and worse timing, which may negate the power savings achieved on the clock tree.

In addition, there are certain constraints of conversion from single-bit to multi-bit. For example, if a bus width is 7-bit, but there is no 7-bit cell available in the library. The EDA tool may attempt to use 8-bit cells, with one bit unused. Therefore, it is not always possible for the conversion, or to achieve the expected power savings.