Chipress

If the design is using only posedge of a single clock, then the clock can be defined as:

# assume clk is the clock input signal name at top level

clock clk

If the design is using only negedge of a clock, then the clock can be defined as:

clock ~clk

It is not uncommon for a design using both posedge and negedge of a clock. For the Jasper Gold to properly evaluate design behavior on both edges of the clock, the clock should be defined as:

clock clk -both_edges

The “-both_edges” option should also be used when there exists high transparent latches in the design.

However, “-both_edges” has a side effect that causes design inputs to toggle at both edges of the clock. For example, if the assumptions on design inputs are defined at posedge of the clock, then the FV tool may not conform to the assumptions at the negedge of the clock, causing illegal stimulus at the next posedge of the clock.

To constrain all the design inputs only change at one edge of the clock, while still allowing the FV tool to analyze design behavior on both edges of the clock, the clock should be defined as:

# all design inputs only change at posedge of the clock
clock -rate -default clk
# all design inputs only change at negedge of the clock
clock -rate -default ~clk

One can configure only a subset of the design inputs are changing at the posedge of a clock, while allowing some other design inputs are changing at the negedge of a clock:

# assume inA, inB, inC are all design inputs sensitive to posedge of the clock
clock -rate [inA, inB, inC] clk
# assume inD, inE, inF are all design inputs sensitive to negedge of the clock
clock -rate [inD, inE, inF] ~clk