Chipress

In our book “Crack the Hardware Interview: Verification, Implementation, Synthesis & Power”, we briefly discussed what to do if FV cannot achieve full proof. Design reduction is an important technique to tackle this problem. We will dive a little deeper in post.

Many designs have parameters for structures that we can reduce, for example, FIFO depth, timeout values, etc.

If the parameter is defined using a Verilog `define directive, it can be overridden during the design analyzing phase. For example, if FIFO depth is defined using directive “`FIFO_DEPTH”, then it can be overridden using the command below:

analyze -sv my_fifo.v +define+FIFO_DEPTH=4

The tool will issue a warning message for each overridden `define.

It is also possible to override the parameter values during the design elaboration phase. For example, if FIFO depth is defined using a parameter “FIFO_DEPTH”, then it can be overridden using the command below:

# override the parameter value in top level
elaborate -parameter top.FIFO_DEPTH 4

# override the parameter value in leaf module
# parameters can be referenced hierarchically
elaborate -parameter top.sub_module.leaf_module.FIFO_DEPTH 4

Designers should use design reduction techniques with caution. After parameter value override, the design behaves differently, and some behaviors may no longer be possible. Bugs caused by the removed behavior will not be caught.

In addition, overriding parameter values may cause elaboration errors. For example, if designers change a parameterized signal width value, the design may no longer be successfully elaborated.

There are 2 more techniques to deal with FV complexity, namely black boxing and abstraction. We will cover these topics in later posts.