Best Practice for RTL Naming Conventions

In this post, we share a few RTL naming conventions for better readability. See the table below.

RTL Naming Convention	RTL Naming Convention
Use intelligible signal / variable names	Better readability is achieved if the RTL code is “self-documented”
Use “<name>_clk” for the name of a module’s clock input
Use “_n” suffix for asserted low signals
Use “<name>_reset_n” for the name of a module’s reset input
Include an “_t” suffix for typedef declarations	For example, typedef struct packed { logic en; logic [2:0] cfg; } mode_t;
Parameters / localparams should use all-caps with underscores	For example, ADDR_WIDTH, DESIGN_TYPE, etc.
Global `define macro should use all-caps characters with underscores and unique identifiers of the form <IP>_<BLK>_<name>	Unless absolutely required, using macros is not recommended; only have macros in RTL when the use of parameters / localparams is not possible
Use the same signal names across hierarchy boundaries	When the signal names keep changing across different levels of hierarchies, it is very difficult to follow a design
Use the exact name, including matching the case of the characters, for variables or parameters derived from specifications and standards	This will be easier to cross reference between RTL code and specifications
APB signals must include prefix “P”, and possibly include a suffix to distinguish different APB interfaces under the same RTL hierarchy	This follows the same naming convention as in APB protocol
AHB signals must include prefix “H”, and possibly include a suffix to distinguish different AHB interfaces under the same RTL hierarchy	This follows the same naming convention as in AHB protocol
AXI signals must include prefixes “A”, “AW”, “W”, “B”, “AR”, “R”, and possibly include a suffix to distinguish different AXI interfaces under the same RTL hierarchy	This follows the same naming convention as in AXI protocol

If not properly following RTL naming conventions, RTL designers can easily make coding mistakes, and create unnecessary troubles when integrating RTL designs at the top level.

Other than RTL naming conventions, there are other places that RTL designers should watch out for when coding RTL. We recommend readers to reference “Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them” for more details.