Chipress

What is Chip Harvesting?

Chip harvesting is a common technique to reduce cost and increase overall yield, by salvaging defective parts of logic or memory. Defective part of the chip will be fuse-isolated from the working parts, and the chip can still be shipped to market and delivered to consumers.

This technique has long been adopted by chip manufactures like Intel. Many CPU dies are made at the same time from a single silicon wafer, but manufacturing CPUs is such a complicated process that some come out defective. For example, a CPU die with 8 cores may have one defective core. Without chip harvesting, that CPU die has to be thrown away. With harvesting, the defective core gets disabled and the CPU die gets sold as a lower-end chip.

Usually yield is less mature in a new technology node. Chip harvesting is particularly important when a new technology node is adopted and yield is slowly improving.

Implementation Considerations for Chip Harvesting?

Design and DFT overhead area needs to be factored in during chip design phase, and certain design considerations must be taken into account:

1. There could be config registers located in defective parts. When defective parts are fuse-isolated / fuse-clamped in real silicon, RTL should return error responses if SW attempts to access those registers. Such implementation can only be done during the RTL design phase.

2. Logic to be harvested shall be clearly defined when designing a chip, and design engineers must insert fuse-isolation / fuse-clamp logic in RTL. Later on, if the part is tested defective, it can be isolated from the rest of the working parts.

3. In terms of DFT, dedicated scan chains or scan codec shall be implemented for harvested logic for defect isolation.

4. Defective parts may be separately clock gated or power gated to save power, and a dedicated clock domain or power domain may be defined for chip harvesting.