Chipress

The following diagram shows a typical Automated Test Equipment (ATE) architecture:

The test program / test pattern is stored in pattern memory, and ATE applies the stimulus per predefined test patterns. ATE then measures DUT response and matches it with the expected response.

The test patterns are generated by tools, not by functional tests, hence Automatic Test Pattern Generation (ATPG). ATPG results in better coverage than functional coverage.

In ATPG, we do not really care what the circuits or gates inside the chip do. Instead, we treat the chip as a bunch of combination gates and sequential logics, assume stuck-at faults at different internal nodes, and find test patterns that can reveal the failing behavior at the internal nodes. We then propagate the internal nodes values to an external pin to observe the outputs.

Combinational logic is easy to control and observe compared to sequential logic. ATPG uses a method called internal scan, or scan-based ASIC testing, to test sequential logic in the design. 

As a side note, in addition to ATPG and scan-based ASIC testing, IDDQ testing is another form of testing to find out if there are manufacturing defects in a chip. For CMOS circuits, there should be very little leakage current flowing through the chip when there is no activity. In IDDQ testing, if there is a large amount of current observed when the chip is not doing anything, then there must be a short-circuit in the chip.

To learn more, we recommend interviewees to study Chapter 3 & 4 of the book “VLSI Test Principles and Architectures: Design for Testability”. It is one of the most comprehensive guides to DFT methodology in the market.