Chipress

ASIC / SOC testability is important during chip fabrication, and fault model is used to represent the effects of a physical defect.

There are quite a few types of fault models, among which the most common ones are stuck-at fault, bridging fault, and open fault:

1. Due to a defect, a pin acts as if stuck high, independent of signal inputs, we say it is a stuck-at-1 fault; due to a defect, a pin acts as if stuck low, independent of signal inputs, we say it is a stuck-at-0 fault
2. When two nodes get connected together / short-circuit, we call it bridging fault
3. An input to a gate floating or output of a gate not connected anywhere, we call it open fault

To learn more, we recommend interviewees to study Chapter 3 & 4 of the book “VLSI Test Principles and Architectures: Design for Testability”. It is one of the most comprehensive guides to DFT methodology in the market.