Chipress

During chip pre-silicon verification, RTL and DV engineers work together to check the functionality of the HDL model of a chip. Engineers utilize simulation, or formal verification, to make sure an SoC is well designed and logically free of errors.

However, silicon may still fail due to physical defects arising from fabrication. Such defects include but are not limited to: processing defects, material defects, time-dependent failures, packaging failures, and FinFET defects.

Silicon defects are not only more difficult to locate, but also much more costly to remedy as chips are packaged and shipped. In addition, silicon defects escaping to customer damage reputation.

Therefore, we need a cost-effective testing strategy to screen out most of the defecting parts at the chip level, i.e., screen the wafers before the dies are packaged and then full testing of the packaged dies on Automated Test Equipment (ATE).

Test program must be thorough enough to prevent defect escapes, and it requires high fault coverage. In addition, test access to chips can only be done through primary I/O ports. Unlike pre-silicon verification, internal probing is not allowed and often not possible in post-silicon ASIC / SOC testing.

DFT engineers often step in and take measures during the chip pre-silicon design phase, such that the chip is testable after fabrication.

To learn more, we recommend interviewees to study Chapter 3 & 4 of the book “VLSI Test Principles and Architectures: Design for Testability”. It is one of the most comprehensive guides to DFT methodology in the market.