Chipress

The DDR memory controller should typically be equipped with RAS features and saving control. We will cover these two topics in this post.

RAS Features

RAS stands for Reliability, Availability, and Serviceability. If there exists data corruption, either internal to the DDR memory controller or the DRAM device, the DDR memory controller should report and log the failure.

Several places inside the DDR memory controller instantiate SRAMs, for example, the Write Data Buffer and the Read Data Reorder Buffer. One possible RAS feature the controller can implement, is SRAM parity check. Once a parity error is detected, the memory controller should assert an interrupt.

The memory controller can generate ECC for data written to the DDR, and check the ECC for data read from DDR. If an ECC error is detected, the memory controller can assert an interrupt, and return error responses on the AXI read data channel.

Power Saving Control

DDR devices offer several power saving modes, including:

1. Power down, which deactivates most IO buffers of the DDR devices. Power down duration is limited by the DRAM refresh window: the DDR controller needs to wake up the DDR device, issue refresh commands, and re-enter power down if no data requests are pending
2. Self refresh, where DDR devices automatically refreshes their banks. Over a relatively long period of time, self refresh saves more power than power down, but it has a higher exit delay

The DDR memory controller can issue power saving commands to DDR devices via:

1. SW control, where the user initiates power saving commands by writing to some control registers. The user needs to issue power saving exit commands by writing to some other control registers, to wake up the DDR devices
2. HW control, where the memory controller can automatically enter a specified power saving mode after a configured number of idle cycles, and exit the power saving mode if there are pending data requests

Separately, the DDR memory controller and the DDR devices can achieve different power states by Dynamic Frequency Change (DFC). For example, certain low performance workloads can use the memory controller with lower frequency, while some other high performance workloads can ask for higher frequency.

The Dynamic Frequency Change (DFC) requires the SW to follow a predefined programing sequence, for example, before the DDR memory controller can serve data requests, SW needs to update the DDR timing parameters for DDR Timing Control.

In addition, DDR4 and LPDDR4 offer Data Bus Inversion (DBI) feature, which aims to reduce DC power consumption by selectively inverting the data bus. If the number of bits driving “0” in the lane is five or more, then the entire byte is inverted, and a ninth bit indicating DBI is asserted low.  This ensures that out of the 8 DQ bits and the 9th DBI bit, at least five bits are “1” during any given transaction. The DDR memory controller may consider implementing DBI in its data bus.