Chipress

We provided an overview of a DDR memory controller architecture in previous posts. One important aspect that impacts the controller architecture, is data hazards handling. Note, the data hazards we discuss here is from AXI master’s perspective.

Write After Write (WAW) hazards can happen, when a DDR write packet resides in the Write Command Pool, and the Write Request Packetizer pushes a new DDR write packet for the same DDR address. If WAW hazards happen, the new DDR write packet should be “merged” with the old one.

If the DDR device does not support partial write and Read-Modify-Write (RMW) is needed, WAW hazards handling requires special care. When a RMW is in flight, a new DDR partial write packet mapped to the same DDR address may be pushed into the Write Command Pool, and be merged with the old one. When the RMW’s read data is back, certain read data shall be dropped, such that it will not override the new DDR partial write data. This also implies the Write Data Buffer should keep data masks / byte enable information for each DDR write packet.

Read After Write (RAW) hazards can happen, when a DDR write packet resides in the Write Command Pool, and the Read Request Packetizer pushes a new DDR read packet for the same DDR address.

If RAW hazards happen with all write data available in the Write Data Buffer, the DDR read packet will get the data through Forward Buffer, and no DDR read command is issued.

If the DDR write packet is a partial write, RAW hazards happen with only partial write data available in the Write Data Buffer. In this case, the Merge Buffer reads data from the Write Data Buffer, merges it with the data read from DDR, and pushes the data into the Read Data Reorder Buffer.

Write After Read (WAR) hazards can be eliminated, if the AXI master enforces the synchronization at source, or the AXI master makes sure it gets the read data response first, before issuing a write request to the same AXI address. The DDR memory controller does not do any special treatment for WAR hazards, and assumes no ordering between AXI read and write channels.

It is easy to see that, since the AXI write response is returned when DDR write packets are pushed into the Write Command Pool, the DDR memory controller needs dedicated pieces of hardware for WAW and RAW hazards. Designers can choose to make trade-offs between hardware complexity and write latency. If the write latency is not an issue, designers can return the AXI write responses after DDR write packets are popped from Write Command Pool, and Write Command Pool merge logic, Merge Buffer and Forward Buffer can all be removed.