Design a sync FIFO using single-port SRAMs

In our 1st book in series “Crack the Hardware Interview”, we discussed how to design a sync FIFO using a dual-port SRAM.

Assuming the same size of storage, single-port SRAMs typically come with a smaller area than dual-port SRAMs. Therefore, using single-port SRAMs as sync FIFO storage is a more common practice and a more preferred design technique.

Using single-port SRAM to implement a sync FIFO has a few challenges:

A sync FIFO can support one read and one write accesses in the same cycle, thus dual-port SRAMs naturally make ends meet; However, single-port SRAMs can only support either one read or one write access in the same cycle clock, and we could have read and write conflict when using single-port SRAMs
Due to its single-port nature, single-port SRAMs can only provide half of the bandwidth / throughput as required by a sync FIFO

One possible solution is to use 2 single-port SRAM instances, where the SRAM data width is the same as FIFO data width. One instance serves accesses to even FIFO addresses, while the other serves the odd.

Even with 2 single-port SRAM instances, it is still possible to have read and write conflicts. For example, in one clock cycle, FIFO write may access address 8, while FIFO read may access address 2, both access the even SRAM instance.

To resolve the conflict issue, we could make read access a higher priority: if both FIFO read and write access the same SRAM instance in the same clock cycle, we delay the write, serve the read first, and serve the write in the next clock cycle. This is OK, as it is impossible to have back-to-back read and write conflicts: for each SRAM instance, we can only have one read every other clock cycle, and one write every other clock cycle.

Once we know how to implement a sync FIFO using a dual-port SRAM, with the above design considerations in mind, we can easily write RTL code for the sync FIFO using single-port SRAMs.