Design a DDR Memory Controller (VI) – DRAM hierarchy & DDR Address Decoding

A typical DRAM hierarchy looks like this:

Channel (CH)
Dual Inline Memory Module (DIMM)
Rank (RA)
Chip (CS)
Bank Group (BG)
Bank (BA)
Row Address (RA)
Column Address (CA)

It is possible that a particular DRAM product does not include one or more hierarchies listed above. For example, DIMM was commonly seen in desktops and servers, not in smart phones or watches; Bank Group (BG) was introduced in DDR4; Channel (CH) was introduced in LPDDR4, etc.

Due to electrical constraints, only a few Channels and DIMMs can be attached to a bus.

Ranks can increase the overall capacity on a DIMM and each rank has multiple chips. Chips will increase the data transfer bandwidth, and multiple chips can be enabled in the same DRAM access.

Multiple Bank Groups and Banks offer memory access parallelism. They are provided so we can be simultaneously working on different requests. Each DRAM request may take a long time to finish, and interleaving Bank Groups / Banks across different requests can hide the long DRAM latency and improve DRAM throughput.

To maximize density, arrays in a Bank are made large, i.e., the rows indexed by Row Addresses are wide. Each array provides a single output pin to the outside, thus the Column Addresses index the bit location within a row.

DRAM Chips are described as xN, where N refers to the number of output pins. A Bank of a xN DRAM Chip internally has N memory arrays.

The diagram below shows one Rank composed of eight x8 DRAM Chips, thus the data bus width of the Rank is 64-bits.

These two blog posts have a great explanation on DDR4 and LPDDR5 physical structure, and both of these posts are recommended reads.

Understanding of DRAM hierarchy is crucial in designing an efficient DDR memory controller. The controller needs to chop the incoming AXI write and read requests into DDR burst aligned packets, and decode the AXI address into the DRAM address. The address decoding logic should properly interleave the AXI traffic, such that DDR bank conflict is minimized and the DDR device can achieve a throughput that is close to its theoretical maximum.

If you want to understand more about DRAM in a systematic way, “DRAM Circuit Design: Fundamental and High-Speed Topics” written by Brent Keeth, R. Jacob Baker, Brian Johnson and Feng Lin would help. In particular, the first 5 chapters of the book are good enough to get a high-level understanding.