Chipress

Our 2nd book in “Crack the Hardware Interview” series focuses on verification, implementation, synthesis and power questions frequently asked during RTL design interviews. We hope you find the information in this book useful in preparing digital design / verification interviews.

To provide a preview of the book, the Table of Contents is shown below:

Part 1 Verification

Chapter 1 Design Verification (DV)

• Q1: What is constrained random regression? Why is constraint review important?
• Q2: How to verify the fairness of a round-robin arbiter?
• Q3: Write a test plan for vending machine design
• Q4: What is code coverage?
• Q5: What is functional coverage? How to write functional coverage?

Chapter 2 Formal Verification (FV)

• Q6: What is FV? How is it different from DV?
• Q7: What are the advantages and disadvantages of FV?
• Q8: What is an immediate assertion? What is a concurrent assertion?
• Q9: What is the overlapping implication? What is the non-overlapping implication?
• Q10: What is formal property verification (FPV)?
• Q11: What if formal property verification (FPV) cannot achieve full proof?
• Q12: What is formal equivalence verification (FEV)?

Part 2 Implementation, Synthesis & Power

Chapter 1 Lint Check

• Q1: What are the most critical errors in lint check?

Chapter 2 Cross Domain Crossing (CDC) Check

• Q2: How to define CDC constraints / SGDC in CDC check?

Chapter 3 Reset Domain Crossing (RDC) Check

• Q3: What are the differences between sync and async reset?
• Q4: What does RDC check do?
• Q5: What are common RDC techniques / schemes?

Chapter 4 Design Constraints (SDC)

• Q6: What are design / library objects? How to access & manipulate these objects?
• Q7: How to set single-clock design constraints?
• Q8: How to set I/O constraints for single-clock design?
• Q9: How to set multi-synchronous-clock design constraints?
• Q10: How to set generated clock design constraints?
• Q11: How to set mutually exclusive synchronous clock design constraints?
• Q12: How to set asynchronous clock design constraints?

Chapter 5 Synthesis

• Q13: What is ZWL synthesis / sanity synthesis?
• Q14: What is topographical synthesis / production synthesis?
• Q15: What are basic setups before running synthesis? How to do “set_app_var” and create milkyway library?
• Q16: What is Design Compiler (DC) synthesis flow? Can you write a simple DC synthesis script?
• Q17: What to check before running synthesis?
• Q18: What are the common DC synthesis optimization techniques?

Chapter 6 Logical Equivalence Check (LEC)

• Q19: What is LEC? Why should we do LEC?
• Q20: What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

Chapter 7 ECO Flow

• Q21: What is ECO? Why is ECO needed?
• Q22: How does functional ECO flow work?

Chapter 8 Power

• Q23: What are static power, dynamic power and short-circuit dissipation power?
• Q24: How to reduce static power, dynamic power, and short-circuit dissipation power?
• Q25: Why are isolation cells required in power aware design?
• Q26: How many types of isolation cells are there?
• Q27: What does a clock gating cell look like?
• Q28: What are the SRAM power states?

Part 3 Front-End Design Checklist